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daniel.kho |
/*
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This file is part of the AXI4 Transactor and Bus Functional Model
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(axi4_tlm_bfm) project:
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http://www.opencores.org/project,axi4_tlm_bfm
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Description
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Synthesisable use case for AXI4 on-chip messaging.
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To Do:
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Author(s):
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- Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com
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Copyright (C) 2012-2013 Authors and OPENCORES.ORG
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This source file may be used and distributed without
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restriction provided that this copyright statement is not
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removed from the file and that any derivative work contains
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the original copyright notice and the associated disclaimer.
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This source file is free software; you can redistribute it
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and/or modify it under the terms of the GNU Lesser General
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Public License as published by the Free Software Foundation;
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either version 2.1 of the License, or (at your option) any
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later version.
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This source is distributed in the hope that it will be
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useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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PURPOSE. See the GNU Lesser General Public License for more
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details.
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You should have received a copy of the GNU Lesser General
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Public License along with this source; if not, download it
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from http://www.opencores.org/lgpl.shtml.
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*/
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library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; use ieee.math_real.all;
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--library tauhop; use tauhop.transactor.all, tauhop.axiTransactor.all; --TODO just use axiTransactor here as transactor should already be wrapped up.
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/* TODO remove once generic packages are supported. */
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library tauhop; use tauhop.tlm.all, tauhop.axiTLM.all;
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/* synthesis translate_off */
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library osvvm; use osvvm.RandomPkg.all; use osvvm.CoveragePkg.all;
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/* synthesis translate_on */
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library altera; use altera.stp;
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entity user is port(
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/* Comment-out for simulation. */
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clk,nReset:in std_ulogic;
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/* AXI Master interface */
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axiMaster_in:in t_axi4StreamTransactor_s2m;
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axiMaster_out:buffer t_axi4StreamTransactor_m2s;
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/* Debug ports. */
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dataIn:in t_msg;
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selTxn:in unsigned(3 downto 0)
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);
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end entity user;
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architecture rtl of user is
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signal reset:std_ulogic:='0';
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signal locked:std_ulogic;
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signal porCnt:unsigned(3 downto 0);
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signal trigger:boolean;
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/* Global counters. */
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constant maxSymbols:positive:=2048; --maximum number of symbols allowed to be transmitted in a frame. Each symbol's width equals tData's width.
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signal symbolsPerTransfer:t_cnt;
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signal outstandingTransactions:t_cnt;
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/* BFM signalling. */
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signal readRequest,writeRequest:t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false);
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signal readResponse,writeResponse:t_bfm;
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type txStates is (idle,transmitting);
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signal txFSM,i_txFSM:txStates;
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/* Tester signals. */
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/* synthesis translate_off */
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signal clk,nReset:std_ulogic:='0';
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attribute period:time; attribute period of clk:signal is 10 ps;
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/* synthesis translate_on */
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signal testerClk:std_ulogic;
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signal dbg_axiTxFSM:axiBfmStatesTx;
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signal anlysr_dataIn:std_logic_vector(255 downto 0);
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signal anlysr_trigger:std_ulogic;
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signal irq_write:std_ulogic; -- clock gating.
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begin
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/* Bus functional models. */
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axiMaster: entity tauhop.axiBfmMaster(rtl)
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port map(
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aclk=>irq_write, n_areset=>not reset,
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readRequest=>readRequest, writeRequest=>writeRequest,
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readResponse=>readResponse, writeResponse=>writeResponse,
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axiMaster_in=>axiMaster_in,
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axiMaster_out=>axiMaster_out,
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symbolsPerTransfer=>symbolsPerTransfer,
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outstandingTransactions=>outstandingTransactions,
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dbg_axiTxFSM=>dbg_axiTxFSM
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);
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/* Interrupt-request generator. */
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trigger<=txFSM/=i_txFSM or writeResponse.trigger;
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irq_write<=clk when not reset else '0';
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/* Simulation Tester. */
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/* PLL to generate tester's clock. */
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f100MHz: entity altera.pll(syn) port map(
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areset=>'0', --not nReset,
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inclk0=>clk,
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c0=>testerClk,
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locked=>locked
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);
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/* synthesis translate_off */
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clk<=not clk after clk'period/2;
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process is begin
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nReset<='1'; wait for 1 ps;
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nReset<='0'; wait for 500 ps;
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nReset<='1';
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wait;
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end process;
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/* synthesis translate_on */
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/* Hardware tester. */
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/* Power-on Reset circuitry. */
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por: process(nReset,clk) is
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--variable porCnt:unsigned(7 downto 0):=(others=>'1');
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begin
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if not nReset then reset<='1'; porCnt<=(others=>'1');
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elsif rising_edge(clk) then
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reset<='0';
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if porCnt>0 then reset<='1'; porCnt<=porCnt-1; end if;
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end if;
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end process por;
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/* Stimuli sequencer. TODO move to tester/stimuli.
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This emulates the AXI4-Stream Slave.
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*/
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/* Simulation-only stimuli sequencer. */
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/* synthesis translate_off */
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process is begin
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report "Performing fast read..." severity note;
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/* Fast read. */
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while not axiMaster_out.tLast loop
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/* Wait for tValid to assert. */
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while not axiMaster_out.tValid loop
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wait until falling_edge(clk);
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end loop;
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axiMaster_in.tReady<=true;
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wait until falling_edge(clk);
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axiMaster_in.tReady<=false;
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end loop;
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wait until falling_edge(clk);
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report "Performing normal read..." severity note;
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/* Normal read. */
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while not axiMaster_out.tLast loop
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/* Wait for tValid to assert. */
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while not axiMaster_out.tValid loop
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wait until falling_edge(clk);
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end loop;
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wait until falling_edge(clk);
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wait until falling_edge(clk);
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axiMaster_in.tReady<=true;
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wait until falling_edge(clk);
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axiMaster_in.tReady<=false;
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wait until falling_edge(clk);
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end loop;
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report "Completed normal read." severity note;
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for i in 0 to 10 loop
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wait until falling_edge(clk);
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end loop;
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/* One-shot read. */
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axiMaster_in.tReady<=true;
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wait until falling_edge(clk);
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axiMaster_in.tReady<=false;
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report "Completed one-shot read." severity note;
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wait;
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end process;
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/* synthesis translate_on */
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sequencer_ns: process(all) is begin
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txFSM<=i_txFSM;
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if reset then txFSM<=idle;
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else
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case i_txFSM is
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when idle=>
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if outstandingTransactions>0 then txFSM<=transmitting; end if;
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when transmitting=>
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if axiMaster_out.tLast then
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txFSM<=idle;
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end if;
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when others=> null;
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end case;
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end if;
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end process sequencer_ns;
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sequencer_op: process(reset,irq_write) is
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/* Local procedures to map BFM signals with the package procedure. */
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procedure read(address:in t_addr) is begin
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read(readRequest,address);
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end procedure read;
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procedure write(data:in t_msg) is begin
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write(request=>writeRequest, address=>(others=>'-'), data=>data);
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end procedure write;
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variable isPktError:boolean;
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/* Tester variables. */
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/* Synthesis-only randomisation. */
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/* Simulation-only randomisation. */
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/* synthesis translate_off */
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variable rv0:RandomPType;
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/* synthesis translate_on */
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begin
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if falling_edge(irq_write) then
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case txFSM is
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when transmitting=>
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if trigger then
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/* synthesis translate_off */
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write(rv0.RandSigned(axiMaster_out.tData'length));
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/* synthesis translate_on */
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case selTxn is
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when x"0"=> write(dataIn);
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when x"1"=> write(32x"12345678");
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when x"2"=> write(32x"87654321");
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when x"3"=> write(32x"abcd1234");
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when others=> write(32x"12ab34cd");
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end case;
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end if;
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when others=>null;
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end case;
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end if;
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end process sequencer_op;
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sequencer_regs: process(irq_write) is begin
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if falling_edge(irq_write) then
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i_txFSM<=txFSM;
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end if;
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end process sequencer_regs;
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outstandingTransactions<=128x"fc";
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end architecture rtl;
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