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[/] [axi4_tlm_bfm/] [trunk/] [rtl/] [quartus-synthesis/] [user.vhdl] - Blame information for rev 17

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1 9 daniel.kho
/*
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        This file is part of the AXI4 Transactor and Bus Functional Model
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        (axi4_tlm_bfm) project:
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                http://www.opencores.org/project,axi4_tlm_bfm
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        Description
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        Synthesisable use case for AXI4 on-chip messaging.
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        To Do:
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        Author(s):
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        - Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com
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        Copyright (C) 2012-2013 Authors and OPENCORES.ORG
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        This source file may be used and distributed without
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        restriction provided that this copyright statement is not
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        removed from the file and that any derivative work contains
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        the original copyright notice and the associated disclaimer.
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        This source file is free software; you can redistribute it
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        and/or modify it under the terms of the GNU Lesser General
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        Public License as published by the Free Software Foundation;
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        either version 2.1 of the License, or (at your option) any
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        later version.
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        This source is distributed in the hope that it will be
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        useful, but WITHOUT ANY WARRANTY; without even the implied
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        warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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        PURPOSE. See the GNU Lesser General Public License for more
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        details.
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        You should have received a copy of the GNU Lesser General
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        Public License along with this source; if not, download it
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        from http://www.opencores.org/lgpl.shtml.
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*/
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library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; use ieee.math_real.all;
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--library tauhop; use tauhop.transactor.all, tauhop.axiTransactor.all;          --TODO just use axiTransactor here as transactor should already be wrapped up.
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/* TODO remove once generic packages are supported. */
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library tauhop; use tauhop.tlm.all, tauhop.axiTLM.all;
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/* synthesis translate_off */
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library osvvm; use osvvm.RandomPkg.all; use osvvm.CoveragePkg.all;
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/* synthesis translate_on */
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library altera; use altera.stp;
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entity user is port(
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        /* Comment-out for simulation. */
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        clk,reset:in std_ulogic;
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        /* AXI Master interface */
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--      axiMaster_in:in t_axi4StreamTransactor_s2m;
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        axiMaster_out:buffer t_axi4StreamTransactor_m2s;
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        /* Debug ports. */
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        selTxn:in unsigned(3 downto 0):=x"0"
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);
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end entity user;
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architecture rtl of user is
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        signal i_reset:std_ulogic:='0';
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        signal porCnt:unsigned(3 downto 0);
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        /* Global counters. */
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        constant maxSymbols:positive:=2048;             --maximum number of symbols allowed to be transmitted in a frame. Each symbol's width equals tData's width. 
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        signal symbolsPerTransfer:t_cnt;
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        signal outstandingTransactions:t_cnt;
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        /* BFM signalling. */
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        signal readRequest,writeRequest:t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false);
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        signal readResponse,writeResponse:t_bfm;
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        /* Tester signals. */
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        /* synthesis translate_off */
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        signal clk,reset:std_ulogic:='0';
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        attribute period:time; attribute period of clk:signal is 10 ps;
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        /* synthesis translate_on */
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        signal dbg_axiTxFSM:axiBfmStatesTx;
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        signal anlysr_dataIn:std_logic_vector(255 downto 0);
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        signal anlysr_trigger:std_ulogic;
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        signal axiMaster_in:t_axi4StreamTransactor_s2m;
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        signal irq_write:std_ulogic;            -- clock gating.
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begin
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        /* Bus functional models. */
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        axiMaster: entity tauhop.axiBfmMaster(rtl)
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                port map(
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                        aclk=>irq_write, n_areset=>not i_reset,
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                        readRequest=>readRequest,       writeRequest=>writeRequest,
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                        readResponse=>readResponse,     writeResponse=>writeResponse,
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                        axiMaster_in=>axiMaster_in,
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                        axiMaster_out=>axiMaster_out,
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                        symbolsPerTransfer=>symbolsPerTransfer,
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                        outstandingTransactions=>outstandingTransactions,
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                        dbg_axiTxFSM=>dbg_axiTxFSM
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        );
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        /* Clocks and reset. */
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        /* Power-on Reset circuitry. */
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        por: process(reset,clk) is begin
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                if reset then i_reset<='1'; porCnt<=(others=>'1');
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                elsif rising_edge(clk) then
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                        i_reset<='0';
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                        if porCnt>0 then i_reset<='1'; porCnt<=porCnt-1; end if;
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                end if;
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        end process por;
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        /* synthesis translate_off */
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        clk<=not clk after clk'period/2;
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        process is begin
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                reset<='0'; wait for 1 ps;
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                reset<='1'; wait for 500 ps;
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                reset<='0';
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                wait;
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        end process;
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        /* synthesis translate_on */
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        /* Simulation Tester. */
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        /* Hardware tester. */
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        bist: entity work.tester(rtl) port map(
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                clk=>clk, reset=>i_reset,
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                axiMaster_in=>axiMaster_in,
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                axiMaster_out=>axiMaster_out,
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                readRequest=>readRequest, writeRequest=>writeRequest,
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                readResponse=>readResponse, writeResponse=>writeResponse,
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                irq_write=>irq_write,
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                symbolsPerTransfer=>symbolsPerTransfer,
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                outstandingTransactions=>outstandingTransactions,
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                selTxn=>selTxn
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        );
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end architecture rtl;

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