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Subversion Repositories bch_configurable

[/] [bch_configurable/] [trunk/] [testbench/] [sim_top.v] - Blame information for rev 4

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1 4 Success105 
`timescale 1ns/100ps
2 
module sim_top;
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4 
 
5 
reg I_clk;
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reg I_rst;
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8 
reg [31:0] S_data_random1 = 0;
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reg [31:0] S_data_random2 = 0;
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reg [31:0] S_data_random3 = 0;
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reg [31:0] S_data_random4 = 0;
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reg S_start_id = 0;
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wire [127:0] S_data_random;
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initial
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begin
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    I_clk = 0;
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        forever #5 I_clk = !I_clk;
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end
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initial
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begin
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        I_rst = 0;
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        #100
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        forever
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        begin
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            @(posedge I_clk);
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                T_random_gen;
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        end
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end
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initial
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begin
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        S_start_id = 0;
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    #120
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        @(posedge I_clk);
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        S_start_id = 1;
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        @(posedge I_clk);
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        S_start_id = 0;
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end
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42 
task T_random_gen;
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begin
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        S_data_random1 = $random;
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        S_data_random2 = $random;
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        S_data_random3 = $random;
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        S_data_random4 = $random;
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end
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endtask
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51 
 
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assign S_data_random = {S_data_random4,S_data_random3,S_data_random2,S_data_random1};
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localparam C_FRAME_LEN = 64;
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genvar S_i;
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generate
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for(S_i=0;S_i<1;S_i=S_i+1)
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begin:test
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localparam C_DWIDTH_THREAD = 2**(S_i+1);
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localparam C_INPUT_NUM = C_DWIDTH_THREAD*C_FRAME_LEN;
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localparam C_COEF_NUM = (S_i<3) ? 15 : 4*(S_i+4);
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localparam C_TOTALBIT_NUM = C_INPUT_NUM + C_COEF_NUM*(S_i+8);
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//localparam C_TOTALBIT_NUM = C_INPUT_NUM + C_COEF_NUM*(S_i+8) - 4; //primpoly8 is not all 8 in genpoly,one in the middle is 4
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localparam C_PRIMPOLY_ORDER = S_i + 8;
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localparam C_GENPOLY = (S_i == 0) ? 'h11d : ((S_i == 1) ? 'h211 : ((S_i == 2) ? 'h409 : ((S_i == 3) ? 'h805 : ((S_i == 4) ? 'h1053 : ((S_i == 5) ? 'h201b : 'h4443)))));
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localparam C_SEARCH_THREAD_NUM = 2**S_i;
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localparam C_BYTE_NUM = C_TOTALBIT_NUM/C_DWIDTH_THREAD;
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localparam C_COEF_NUM2 = C_COEF_NUM;
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wire [C_DWIDTH_THREAD-1:0] S_data;
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reg [C_DWIDTH_THREAD-1:0] S_data_d;
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wire S_data_v;
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wire S_data_sof;
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wire S_data_eof;
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reg S_data_v_d;
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reg S_data_sof_d;
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reg S_data_eof_d;
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wire [1:0] S_result;
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reg I_data_v;
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reg I_data_sof;
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reg I_data_eof;
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integer S_err_byte [C_COEF_NUM2-1 : 0];
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reg [C_DWIDTH_THREAD-1:0] S_err_bit [C_COEF_NUM2-1 : 0] ;
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integer S_err_num;
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86 
reg [7:0] S_encode_cnt = 0;
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reg [7:0] S_cnt = 0;
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reg S_data_v_2d = 0;
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90 
test_bch_encode
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#(
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.C_DWIDTH         (C_DWIDTH_THREAD        ),
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.C_COEF_NUM       (C_COEF_NUM      ),
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.C_PRIMPOLY_ORDER (C_PRIMPOLY_ORDER),
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.C_PRIM_POLY      (C_GENPOLY       )
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)
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test_bch_encode_inst
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(
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.I_clk       (I_clk      ),
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.I_rst       (I_rst      ),
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.I_data      (S_data_random[C_DWIDTH_THREAD-1:0]),
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.I_data_v    (I_data_v   ),
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.I_data_sof  (I_data_sof ),
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.I_data_eof  (I_data_eof ),
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.O_data      (S_data     ),
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.O_data_v    (S_data_v   ),
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.O_data_sof  (S_data_sof ),
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.O_data_eof  (S_data_eof )
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);
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always @(posedge I_clk)
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begin
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    if(S_start_id || S_result[1] || S_cnt != 0)
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        begin
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            if(S_cnt == C_FRAME_LEN)
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                    S_cnt <= 'd0;
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                else
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                    S_cnt <= S_cnt + 'd1;
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        end
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end
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always @(posedge I_clk)
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begin
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    I_data_v <= (S_cnt != 'd0);
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        I_data_sof <= S_cnt == 'd1;
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        I_data_eof <= S_cnt == C_FRAME_LEN;
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end
128 
 
129 
integer ii;
130 
 
131 
initial
132 
begin
133 
        forever
134 
        begin
135 
    wait(I_data_sof || S_result[1]);
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        S_err_num = {$random}%C_COEF_NUM;
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        for(ii=0;ii<C_COEF_NUM2;ii=ii+1)
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        begin
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        S_err_byte[ii] = {$random}%C_BYTE_NUM;
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        S_err_bit[ii] = 1<<({$random}%C_DWIDTH_THREAD);
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        end
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        @(posedge I_clk);
143 
        end
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end
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146 
integer jj;
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148 
always @(posedge I_clk)
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begin
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    if(S_data_v)
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                S_encode_cnt <= S_encode_cnt + 'd1;
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        else
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            S_encode_cnt <= 'd0;
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end
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always @(posedge I_clk)
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begin
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    if(S_data_v)
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        begin
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                S_data_d = S_data;
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            for(jj=0;jj<C_COEF_NUM2;jj=jj+1)
162 
                begin
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                        if(S_encode_cnt==S_err_byte[jj])
164 
                                S_data_d = S_data ^ S_err_bit[jj];
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                end
166 
        end
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end
168 
 
169 
always @(posedge I_clk)
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begin
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    S_data_sof_d <= S_data_sof;
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        S_data_eof_d <= S_data_eof;
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        S_data_v_d <= S_data_v;
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        S_data_v_2d <= S_data_v_d;
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end
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177 
tb_encode
178 
#(
179 
.C_DWIDTH            (C_DWIDTH_THREAD),
180 
.C_COEF_NUM          (C_COEF_NUM),
181 
.C_PRIMPOLY_ORDER    (C_PRIMPOLY_ORDER),
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.C_GENPOLY           (C_GENPOLY),
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.C_INPUT_NUM         (C_INPUT_NUM),
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.C_SEARCH_THREAD_NUM (C_SEARCH_THREAD_NUM),
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.C_TOTALBIT_NUM      (C_TOTALBIT_NUM)
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)
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tb_encode_inst
188 
(
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.I_clk                     (I_clk),
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.I_rst                     (I_rst),
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.I_data                    (S_data_d),
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.I_data_v                  (S_data_v_d),
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.I_data_sof                (S_data_sof_d),
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.I_data_eof                (S_data_eof_d),
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.I_data_ori                (S_data_random[C_DWIDTH_THREAD-1:0]),
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.I_data_v_ori              (I_data_v),
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.I_data_sof_ori            (I_data_sof),
198 
.I_data_eof_ori            (I_data_eof),
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.O_result                  (S_result)
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);
201 
integer fid1;
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integer fid2;
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initial
204 
begin
205 
    fid1 = $fopen("data1.txt");
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        fid2 = $fopen("data2.txt");
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end
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always @(posedge I_clk)
209 
begin
210 
    if(S_data_v_2d)
211 
                $fdisplay(fid1,"%d",S_data_d);
212 
        if(I_data_v)
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            $fdisplay(fid2,"%d",S_data_random[C_DWIDTH_THREAD-1:0]);
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end
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216 
always @(posedge I_clk)
217 
begin
218 
    if(S_result[1])
219 
        begin
220 
                $display("width is %d,input number is %d,C_COEF_NUM is %d,total number is %d,prime order is %d,search thread is %d",C_DWIDTH_THREAD,C_INPUT_NUM,C_COEF_NUM,C_TOTALBIT_NUM,C_PRIMPOLY_ORDER,C_SEARCH_THREAD_NUM);
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            if(S_result[0])
222 
                        begin
223 
                                $display("bch is right");
224 
                        end
225 
                else
226 
                        begin
227 
                                $display("bch is wrong");
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                                $stop();
229 
                        end
230 
        end
231 
end
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233 
end
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endgenerate
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endmodule

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