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[/] [bch_configurable/] [trunk/] [testbench/] [tb_encode.v] - Blame information for rev 4

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1 4 Success105 
`timescale 1ns/100ps
2 
module tb_encode
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#(
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parameter C_DWIDTH = 32,
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parameter C_COEF_NUM = 2,
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parameter C_PRIMPOLY_ORDER = 10,
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parameter C_GENPOLY = 'h409,
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parameter C_INPUT_NUM = 512,
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parameter C_SEARCH_THREAD_NUM = 32,
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parameter C_TOTALBIT_NUM = 100
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)
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(
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input I_clk                      ,
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input I_rst                      ,
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input [C_DWIDTH-1:0] I_data      ,
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input I_data_v                   ,
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input I_data_sof                 ,
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input I_data_eof                 ,
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input [C_DWIDTH-1:0] I_data_ori  ,
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input I_data_v_ori               ,
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input I_data_sof_ori             ,
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input I_data_eof_ori             ,
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output reg [1:0] O_result
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);
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wire [C_DWIDTH-1:0] S_data  ;
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wire [C_DWIDTH-1:0] S_data_d;
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wire S_data_v               ;
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wire S_data_sof             ;
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wire S_data_eof             ;
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wire [C_PRIMPOLY_ORDER*C_COEF_NUM-1:0] S_syndrome;
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wire S_syndrome_v;
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wire [C_PRIMPOLY_ORDER*C_COEF_NUM-1+C_PRIMPOLY_ORDER:0] S_err_pos;
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wire [C_SEARCH_THREAD_NUM-1:0] S_ecc;
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wire S_ecc_v;
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wire S_ecc_sof;
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wire S_ecc_eof;
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wire [C_DWIDTH-1:0] S_data_cor;
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wire S_data_v_cor;
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wire S_data_sof_cor;
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wire S_data_eof_cor;
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reg [C_DWIDTH-1:0] S_ram_ori [1023:0];
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reg [9:0] S_ram_ori_waddr = 0;
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reg [9:0] S_ram_ori_raddr = 0;
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reg S_data_eof_cor_d = 0;
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reg [C_DWIDTH-1:0] S_ram_ori_dout = 0;
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reg S_data_v_cor_d = 0;
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reg [C_DWIDTH-1:0] S_data_cor_d = 0;
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reg S_data_eof_ori = 0;
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always @(posedge I_clk)
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begin
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        S_data_eof_ori <= I_data_eof_ori;
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    if(S_data_eof_ori)
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            S_ram_ori_waddr <= 'd0;
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        else if(I_data_v_ori)
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            S_ram_ori_waddr <= S_ram_ori_waddr + 'd1;
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        if(I_data_v_ori)
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            S_ram_ori[S_ram_ori_waddr] <= I_data_ori;
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end
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always @(posedge I_clk)
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begin
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        S_data_eof_cor_d <= S_data_eof_cor;
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    if(S_data_eof_cor_d)
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            S_ram_ori_raddr <= 'd0;
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        else if(S_data_v_cor)
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            S_ram_ori_raddr <= S_ram_ori_raddr + 'd1;
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        S_ram_ori_dout <= S_ram_ori[S_ram_ori_raddr];
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        S_data_v_cor_d <= S_data_v_cor;
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        S_data_cor_d <= S_data_cor;
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end
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always @(posedge I_clk)
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begin
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        if(S_data_sof_cor)
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            O_result[0] <= 1'b1;
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    else if(S_data_v_cor_d)
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            O_result[0] <= O_result[0] && (S_ram_ori_dout == S_data_cor_d);
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        O_result[1] <= S_data_eof_cor_d;
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end
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/*test_bch_encode
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#(
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.C_DWIDTH         (C_DWIDTH        ),
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.C_COEF_NUM       (C_COEF_NUM      ),
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.C_PRIMPOLY_ORDER (C_PRIMPOLY_ORDER),
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.C_PRIM_POLY      (C_GENPOLY       )
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)
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test_bch_encode_inst
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(
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.I_clk       (I_clk      ),
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.I_rst       (I_rst      ),
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.I_data      (I_data     ),
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.I_data_v    (I_data_v   ),
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.I_data_sof  (I_data_sof ),
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.I_data_eof  (I_data_eof ),
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.O_data      (S_data     ),
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.O_data_v    (S_data_v   ),
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.O_data_sof  (S_data_sof ),
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.O_data_eof  (S_data_eof )
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);*/
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test_bch_syndrome
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#(
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.C_DWIDTH             (C_DWIDTH),
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.C_COEF_NUM           (C_COEF_NUM),
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.C_PRIMPOLY_ORDER     (C_PRIMPOLY_ORDER),
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.C_PRIM_POLY          (C_GENPOLY)
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)
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test_bch_syndrome_inst
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(
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.I_clk          (I_clk),
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.I_rst          (I_rst),
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.I_data         (I_data    ),
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.I_data_v       (I_data_v  ),
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.I_data_sof     (I_data_sof),
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.I_data_eof     (I_data_eof),
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.O_syndrome     (S_syndrome),
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.O_syndrome_v   (S_syndrome_v)
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);
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test_bch_bm
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#(
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.C_PRIMPOLY_ORDER  (C_PRIMPOLY_ORDER),
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.C_COEF_NUM        (C_COEF_NUM),
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.C_PRIMPOLY        (C_GENPOLY)
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)
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test_bch_bm_inst
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(
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.I_clk          (I_clk),
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.I_rst          (I_rst),
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.I_syndrome     (S_syndrome),
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.I_syndrome_v   (S_syndrome_v),
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.O_err_pos      (S_err_pos),
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.O_err_pos_v    (S_err_pos_v)
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);
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test_chian_search
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#(
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.C_PRIMPOLY_ORDER (C_PRIMPOLY_ORDER),
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.C_COEF_NUM       (C_COEF_NUM),
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.C_TOTALBIT_NUM   (C_TOTALBIT_NUM),
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.C_THREAD_NUM     (C_SEARCH_THREAD_NUM),
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.C_PRIMPOLY       (C_GENPOLY)
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)
148 
test_chian_search_inst
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(
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.I_clk        (I_clk),
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.I_rst        (I_rst),
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.I_coef       (S_err_pos),
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.I_coef_v     (S_err_pos_v),
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.O_data       (S_ecc    ),
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.O_data_v     (S_ecc_v  ),
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.O_data_sof   (S_ecc_sof),
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.O_data_eof   (S_ecc_eof)
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);
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test_correct
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#(
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.C_INPUT_NUM (C_INPUT_NUM),
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.C_DWIDTH    (C_DWIDTH ),
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.C_ECCWIDTH  (C_SEARCH_THREAD_NUM )
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)
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test_correct_inst
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(
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.I_clk        (I_clk),
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.I_rst        (I_rst),
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.I_data       (I_data  ),
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.I_data_sof   (I_data_sof  ),
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.I_data_eof   (I_data_eof),
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.I_data_v     (I_data_v),
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.I_ecc        (S_ecc    ),
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.I_ecc_v      (S_ecc_v  ),
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.I_ecc_sof    (S_ecc_sof),
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.I_ecc_eof    (S_ecc_eof),
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.O_data       (S_data_cor    ),
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.O_data_v     (S_data_v_cor  ),
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.O_data_sof   (S_data_sof_cor),
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.O_data_eof   (S_data_eof_cor)
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);
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endmodule

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