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[/] [bilinear_demosaic/] [trunk/] [sim/] [rtl_sim/] [registerDelay.v] - Blame information for rev 2

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/* Register delay
q is a registered version of d, registered 'STAGES' times.
Clock enable with 'enable'
*/
 
`default_nettype none
 
module registerDelay #(
        parameter DATA_WIDTH = 8,
        parameter STAGES = 1
)(
        input wire clk, rst, enable,
        input wire [(DATA_WIDTH-1):0] d,
        output wire [(DATA_WIDTH-1):0] q
);
 
        reg [DATA_WIDTH*STAGES-1:0] delayReg;
        assign q = delayReg[DATA_WIDTH-1:0];
 
        always @(posedge clk or posedge rst)
        begin
                if(rst)
                begin
                        delayReg[DATA_WIDTH*STAGES-1:DATA_WIDTH*(STAGES-1)] <= {DATA_WIDTH{1'b0}};
                end
                else
                begin
                        if(enable)
                        begin
                                delayReg[DATA_WIDTH*STAGES-1:DATA_WIDTH*(STAGES-1)] <= d;
                        end
                end
        end
 
        generate
        genvar i;
                for(i = 0; i < (STAGES-1); i = i + 1)
                        begin : rd_generate
                                always @(posedge clk or posedge rst)
                                begin
                                        if(rst)
                                        begin
                                                delayReg[DATA_WIDTH*(i+1)-1:DATA_WIDTH*i] <= {DATA_WIDTH*{1'b0}};
                                        end
                                        else
                                        begin
                                                if(enable)
                                                begin
                                                        delayReg[DATA_WIDTH*(i+1)-1:DATA_WIDTH*i] <= delayReg[DATA_WIDTH*(i+2)-1:DATA_WIDTH*(i+1)];
                                                end
                                        end
                                end
                        end
        endgenerate
endmodule
 
`default_nettype wire

Line No.	Rev	Author	Line
1	2	tesla500	`/* Register delay`
2			`q is a registered version of d, registered 'STAGES' times.`
3			`Clock enable with 'enable'`
4			`*/`
5
6			`default_nettype none
7
8			`module registerDelay #(`
9			`parameter DATA_WIDTH = 8,`
10			`parameter STAGES = 1`
11			`)(`
12			`input wire clk, rst, enable,`
13			`input wire [(DATA_WIDTH-1):0] d,`
14			`output wire [(DATA_WIDTH-1):0] q`
15			`);`
16
17			`reg [DATA_WIDTH*STAGES-1:0] delayReg;`
18			`assign q = delayReg[DATA_WIDTH-1:0];`
19
20			`always @(posedge clk or posedge rst)`
21			`begin`
22			`if(rst)`
23			`begin`
24			`delayReg[DATA_WIDTHSTAGES-1:DATA_WIDTH(STAGES-1)] <= {DATA_WIDTH{1'b0}};`
25			`end`
26			`else`
27			`begin`
28			`if(enable)`
29			`begin`
30			`delayReg[DATA_WIDTHSTAGES-1:DATA_WIDTH(STAGES-1)] <= d;`
31			`end`
32			`end`
33			`end`
34
35			`generate`
36			`genvar i;`
37			`for(i = 0; i < (STAGES-1); i = i + 1)`
38			`begin : rd_generate`
39			`always @(posedge clk or posedge rst)`
40			`begin`
41			`if(rst)`
42			`begin`
43			`delayReg[DATA_WIDTH(i+1)-1:DATA_WIDTHi] <= {DATA_WIDTH*{1'b0}};`
44			`end`
45			`else`
46			`begin`
47			`if(enable)`
48			`begin`
49			`delayReg[DATA_WIDTH(i+1)-1:DATA_WIDTHi] <= delayReg[DATA_WIDTH(i+2)-1:DATA_WIDTH(i+1)];`
50			`end`
51			`end`
52			`end`
53			`end`
54			`endgenerate`
55			`endmodule`
56
57			`default_nettype wire

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[/] [bilinear_demosaic/] [trunk/] [sim/] [rtl_sim/] [registerDelay.v] - Blame information for rev 2