| 1 |
3 |
nuxi1209 |
-------------------------------------------------------------------
|
| 2 |
|
|
-- --
|
| 3 |
|
|
-- Copyright (C) 2013 Author and VariStream Studio --
|
| 4 |
|
|
-- Author : Yu Peng --
|
| 5 |
|
|
-- --
|
| 6 |
|
|
-- This source file may be used and distributed without --
|
| 7 |
|
|
-- restriction provided that this copyright statement is not --
|
| 8 |
|
|
-- removed from the file and that any derivative work contains --
|
| 9 |
|
|
-- the original copyright notice and the associated disclaimer. --
|
| 10 |
|
|
-- --
|
| 11 |
|
|
-- This source file is free software; you can redistribute it --
|
| 12 |
|
|
-- and/or modify it under the terms of the GNU Lesser General --
|
| 13 |
|
|
-- Public License as published by the Free Software Foundation; --
|
| 14 |
|
|
-- either version 2.1 of the License, or (at your option) any --
|
| 15 |
|
|
-- later version. --
|
| 16 |
|
|
-- --
|
| 17 |
|
|
-- This source is distributed in the hope that it will be --
|
| 18 |
|
|
-- useful, but WITHOUT ANY WARRANTY; without even the implied --
|
| 19 |
|
|
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR --
|
| 20 |
|
|
-- PURPOSE. See the GNU Lesser General Public License for more --
|
| 21 |
|
|
-- details. --
|
| 22 |
|
|
-- --
|
| 23 |
|
|
-- You should have received a copy of the GNU Lesser General --
|
| 24 |
|
|
-- Public License along with this source; if not, download it --
|
| 25 |
|
|
-- from http://www.opencores.org/lgpl.shtml --
|
| 26 |
|
|
-- --
|
| 27 |
|
|
-------------------------------------------------------------------
|
| 28 |
2 |
nuxi1209 |
|
| 29 |
|
|
library IEEE;
|
| 30 |
|
|
use IEEE.STD_LOGIC_1164.ALL;
|
| 31 |
|
|
use IEEE.std_logic_unsigned.all;
|
| 32 |
|
|
use IEEE.std_logic_arith.all;
|
| 33 |
|
|
use IEEE.NUMERIC_STD.ALL;
|
| 34 |
|
|
use work.sha_256_pkg.ALL;
|
| 35 |
|
|
|
| 36 |
|
|
entity btc_dsha is
|
| 37 |
|
|
generic(
|
| 38 |
|
|
gBASE_DELAY : integer := 1
|
| 39 |
|
|
);
|
| 40 |
|
|
port(
|
| 41 |
3 |
nuxi1209 |
iRst_async : in std_logic := '0';
|
| 42 |
|
|
|
| 43 |
2 |
nuxi1209 |
iClkReg : in std_logic := '0';
|
| 44 |
|
|
iClkProcess : in std_logic := '0';
|
| 45 |
|
|
|
| 46 |
|
|
iValid_p : in std_logic := '0';
|
| 47 |
|
|
ivAddr : in std_logic_vector(3 downto 0) := (others=>'0');
|
| 48 |
|
|
ivData : in std_logic_vector(31 downto 0) := (others=>'0');
|
| 49 |
|
|
|
| 50 |
|
|
oReachEnd : out std_logic := '0';
|
| 51 |
|
|
oFoundNonce : out std_logic := '0';
|
| 52 |
|
|
ovNonce : out std_logic_vector(31 downto 0) := (others=>'0');
|
| 53 |
|
|
ovDigest : out tDwordArray(0 to 7) := (others=>(others=>'0'))
|
| 54 |
|
|
);
|
| 55 |
|
|
end btc_dsha;
|
| 56 |
|
|
|
| 57 |
|
|
architecture behavioral of btc_dsha is
|
| 58 |
|
|
component pipelines_without_reset IS
|
| 59 |
|
|
GENERIC (gBUS_WIDTH : integer := 1; gNB_PIPELINES: integer range 1 to 255 := 2);
|
| 60 |
|
|
PORT(
|
| 61 |
|
|
iClk : IN STD_LOGIC;
|
| 62 |
|
|
iInput : IN STD_LOGIC;
|
| 63 |
|
|
ivInput : IN STD_LOGIC_VECTOR(gBUS_WIDTH-1 downto 0);
|
| 64 |
|
|
oDelayed_output : OUT STD_LOGIC;
|
| 65 |
|
|
ovDelayed_output : OUT STD_LOGIC_VECTOR(gBUS_WIDTH-1 downto 0)
|
| 66 |
|
|
);
|
| 67 |
|
|
END component;
|
| 68 |
|
|
|
| 69 |
|
|
component edgedtc is port
|
| 70 |
|
|
(
|
| 71 |
|
|
iD : in std_logic;
|
| 72 |
|
|
iClk : in std_logic;
|
| 73 |
|
|
iResetSync_Clk : in std_logic;
|
| 74 |
|
|
iEdge : in std_logic;
|
| 75 |
|
|
oQ : out std_logic := '0'
|
| 76 |
|
|
);
|
| 77 |
|
|
end component;
|
| 78 |
|
|
|
| 79 |
|
|
component sha_256_chunk is
|
| 80 |
|
|
generic(
|
| 81 |
|
|
gMSG_IS_CONSTANT : std_logic_vector(0 to 15) := (others=>'1');
|
| 82 |
|
|
gH_IS_CONST : std_logic_vector(0 to 7) := (others=>'1');
|
| 83 |
|
|
gBASE_DELAY : integer := 3;
|
| 84 |
|
|
gOUT_VALID_GEN : boolean := false;
|
| 85 |
|
|
gUSE_BRAM_AS_LARGE_SHIFTREG : boolean := false
|
| 86 |
|
|
);
|
| 87 |
|
|
port(
|
| 88 |
|
|
iClk : in std_logic := '0';
|
| 89 |
|
|
iRst_async : in std_logic := '0';
|
| 90 |
|
|
|
| 91 |
|
|
iValid : in std_logic := '0';
|
| 92 |
|
|
|
| 93 |
|
|
ivMsgDword : in tDwordArray(0 to 15) := (others=>(others=>'0'));
|
| 94 |
|
|
|
| 95 |
|
|
ivH0 : in std_logic_vector(31 downto 0) := (others=>'0');
|
| 96 |
|
|
ivH1 : in std_logic_vector(31 downto 0) := (others=>'0');
|
| 97 |
|
|
ivH2 : in std_logic_vector(31 downto 0) := (others=>'0');
|
| 98 |
|
|
ivH3 : in std_logic_vector(31 downto 0) := (others=>'0');
|
| 99 |
|
|
ivH4 : in std_logic_vector(31 downto 0) := (others=>'0');
|
| 100 |
|
|
ivH5 : in std_logic_vector(31 downto 0) := (others=>'0');
|
| 101 |
|
|
ivH6 : in std_logic_vector(31 downto 0) := (others=>'0');
|
| 102 |
|
|
ivH7 : in std_logic_vector(31 downto 0) := (others=>'0');
|
| 103 |
|
|
|
| 104 |
|
|
ovH0 : out std_logic_vector(31 downto 0) := (others=>'0');
|
| 105 |
|
|
ovH1 : out std_logic_vector(31 downto 0) := (others=>'0');
|
| 106 |
|
|
ovH2 : out std_logic_vector(31 downto 0) := (others=>'0');
|
| 107 |
|
|
ovH3 : out std_logic_vector(31 downto 0) := (others=>'0');
|
| 108 |
|
|
ovH4 : out std_logic_vector(31 downto 0) := (others=>'0');
|
| 109 |
|
|
ovH5 : out std_logic_vector(31 downto 0) := (others=>'0');
|
| 110 |
|
|
ovH6 : out std_logic_vector(31 downto 0) := (others=>'0');
|
| 111 |
|
|
ovH7 : out std_logic_vector(31 downto 0) := (others=>'0');
|
| 112 |
|
|
|
| 113 |
|
|
oValid : out std_logic := '0'
|
| 114 |
|
|
);
|
| 115 |
|
|
end component;
|
| 116 |
|
|
|
| 117 |
|
|
component HandShake is port
|
| 118 |
|
|
(
|
| 119 |
|
|
iResetSync_Clk : in std_logic; -- Active Hi Reset
|
| 120 |
|
|
iClk : in std_logic; -- Clock
|
| 121 |
|
|
|
| 122 |
|
|
iExternalDemand : in std_logic; -- Async External Demand : one positive pulse
|
| 123 |
|
|
oInternalDemand : out std_logic; -- Sync with iClk Internal demand
|
| 124 |
|
|
iInternalClrDemand : in std_logic -- Clr Internal Demand
|
| 125 |
|
|
);
|
| 126 |
|
|
end component;
|
| 127 |
|
|
|
| 128 |
|
|
component SyncReset is
|
| 129 |
|
|
port(
|
| 130 |
|
|
iClk : in std_logic; -- Clock domain that the reset should be resynchronyze to
|
| 131 |
|
|
iAsyncReset : in std_logic; -- Asynchronous reset that should be resynchronyse
|
| 132 |
|
|
oSyncReset : out std_logic -- Synchronous reset output
|
| 133 |
|
|
);
|
| 134 |
|
|
end component;
|
| 135 |
|
|
|
| 136 |
|
|
constant cCMD_ADDR : std_logic_vector(3 downto 0) := X"D";
|
| 137 |
|
|
constant cCMD_START : std_logic_vector(15 downto 0) := X"0001";
|
| 138 |
|
|
|
| 139 |
|
|
constant cPROCESS_DEALY : std_logic_vector(15 downto 0) := conv_std_logic_vector(64 * gBASE_DELAY * 2 + 1, 16);
|
| 140 |
|
|
constant cCMP_DELAY : std_logic_vector(15 downto 0) := conv_std_logic_vector(64 * gBASE_DELAY * 2 + 1 + 2, 16);
|
| 141 |
|
|
|
| 142 |
|
|
type tProcessStateMachine is (stIdle, stSearch); --, stFound, stNone);
|
| 143 |
|
|
|
| 144 |
|
|
signal sReset_syncProcess : std_logic := '0';
|
| 145 |
|
|
|
| 146 |
|
|
signal svMidState : tDwordArray(0 to 7) := (others=>(others=>'0'));
|
| 147 |
|
|
signal svMerkleRootDword7 : std_logic_vector(31 downto 0) := (others=>'0');
|
| 148 |
|
|
signal svTimeStamp : std_logic_vector(31 downto 0) := (others=>'0');
|
| 149 |
|
|
signal svTargetBits : std_logic_vector(31 downto 0) := (others=>'0');
|
| 150 |
|
|
signal svTargetIndex : std_logic_vector(7 downto 0) := (others=>'0');
|
| 151 |
|
|
signal svTargetFraction : std_logic_vector(23 downto 0) := (others=>'0');
|
| 152 |
|
|
|
| 153 |
|
|
signal svH : tDwordArray(0 to 7) := (others=>(others=>'0'));
|
| 154 |
|
|
|
| 155 |
|
|
signal svStage1MsgDword : tDwordArray(0 to 15) := (others=>(others=>'0'));
|
| 156 |
|
|
signal svStage1Digest : tDwordArray(0 to 7) := (others=>(others=>'0'));
|
| 157 |
|
|
|
| 158 |
|
|
signal svStage2MsgDword : tDwordArray(0 to 15) := (others=>(others=>'0'));
|
| 159 |
|
|
|
| 160 |
|
|
signal svStartNonce : std_logic_vector(31 downto 0) := (others=>'0');
|
| 161 |
|
|
signal svEndNonce : std_logic_vector(31 downto 0) := (others=>'0');
|
| 162 |
|
|
signal svNonce : std_logic_vector(31 downto 0) := (others=>'0');
|
| 163 |
|
|
signal svCmd : std_logic_vector(15 downto 0) := (others=>'0');
|
| 164 |
|
|
signal sCmdValid_syncReg_p : std_logic := '0';
|
| 165 |
|
|
signal sCmdStart_syncReg_p : std_logic := '0';
|
| 166 |
|
|
signal sCmdStart_syncProcess_p : std_logic := '0';
|
| 167 |
|
|
signal sCmdStart_syncProcess_p_1d : std_logic := '0';
|
| 168 |
|
|
|
| 169 |
|
|
signal sProcess : tProcessStateMachine := stIdle;
|
| 170 |
|
|
signal svProcessDelayCnt : std_logic_vector(15 downto 0) := (others=>'0');
|
| 171 |
|
|
signal sProcessOutValid : std_logic := '0';
|
| 172 |
|
|
signal sProcessOutValid_1d : std_logic := '0';
|
| 173 |
|
|
signal sProcessOutValid_2d : std_logic := '0';
|
| 174 |
|
|
signal svCmpNounce : std_logic_vector(31 downto 0) := (others=>'0');
|
| 175 |
|
|
signal svProcessNounce_1d : std_logic_vector(31 downto 0) := (others=>'0');
|
| 176 |
|
|
signal svProcessNounce_2d : std_logic_vector(31 downto 0) := (others=>'0');
|
| 177 |
|
|
|
| 178 |
|
|
|
| 179 |
|
|
signal svStage2DigestBig : std_logic_vector(255 downto 0) := (others=>'0');
|
| 180 |
|
|
signal svStage2DigestLittle : std_logic_vector(255 downto 0) := (others=>'0');
|
| 181 |
|
|
signal svDigestIsZero : std_logic_vector(31 downto 0) := (others=>'0');
|
| 182 |
|
|
signal svDigestSignificant : std_logic_vector(23 downto 0) := (others=>'0');
|
| 183 |
|
|
signal sDigestHighBitsZero : std_logic := '0';
|
| 184 |
|
|
signal sDigestSignificantFit : std_logic := '0';
|
| 185 |
|
|
signal svCmpDelayCnt : std_logic_vector(15 downto 0) := (others=>'0');
|
| 186 |
|
|
signal sCmpResultValid : std_logic := '0';
|
| 187 |
|
|
signal sFoundNonceToIdle : std_logic := '0';
|
| 188 |
|
|
signal sReachEndToIdle : std_logic := '0';
|
| 189 |
|
|
|
| 190 |
|
|
begin
|
| 191 |
3 |
nuxi1209 |
|
| 192 |
2 |
nuxi1209 |
SyncReset_inst_Process : SyncReset
|
| 193 |
|
|
port map(
|
| 194 |
|
|
iClk => iClkProcess,
|
| 195 |
|
|
iAsyncReset => iRst_async,
|
| 196 |
|
|
oSyncReset => sReset_syncProcess
|
| 197 |
|
|
);
|
| 198 |
|
|
|
| 199 |
|
|
process(iClkReg)
|
| 200 |
|
|
begin
|
| 201 |
|
|
if rising_edge(iClkReg) then
|
| 202 |
|
|
if iValid_p = '1' then
|
| 203 |
|
|
case ivAddr is
|
| 204 |
|
|
when X"0" =>
|
| 205 |
|
|
svMidState(0) <= ivData;
|
| 206 |
|
|
|
| 207 |
|
|
when X"1" =>
|
| 208 |
|
|
svMidState(1) <= ivData;
|
| 209 |
|
|
|
| 210 |
|
|
when X"2" =>
|
| 211 |
|
|
svMidState(2) <= ivData;
|
| 212 |
|
|
|
| 213 |
|
|
when X"3" =>
|
| 214 |
|
|
svMidState(3) <= ivData;
|
| 215 |
|
|
|
| 216 |
|
|
when X"4" =>
|
| 217 |
|
|
svMidState(4) <= ivData;
|
| 218 |
|
|
|
| 219 |
|
|
when X"5" =>
|
| 220 |
|
|
svMidState(5) <= ivData;
|
| 221 |
|
|
|
| 222 |
|
|
when X"6" =>
|
| 223 |
|
|
svMidState(6) <= ivData;
|
| 224 |
|
|
|
| 225 |
|
|
when X"7" =>
|
| 226 |
|
|
svMidState(7) <= ivData;
|
| 227 |
|
|
|
| 228 |
|
|
when X"8" =>
|
| 229 |
|
|
svMerkleRootDword7 <= ivData;
|
| 230 |
|
|
|
| 231 |
|
|
when X"9" =>
|
| 232 |
|
|
svTimeStamp <= ivData;
|
| 233 |
|
|
|
| 234 |
|
|
when X"A" =>
|
| 235 |
|
|
svTargetBits <= ivData;
|
| 236 |
|
|
|
| 237 |
|
|
when X"B" =>
|
| 238 |
|
|
svStartNonce(31 downto 0) <= ivData;
|
| 239 |
|
|
|
| 240 |
|
|
when X"C" =>
|
| 241 |
|
|
svEndNonce(31 downto 0) <= ivData;
|
| 242 |
|
|
|
| 243 |
|
|
when cCMD_ADDR =>
|
| 244 |
|
|
svCmd <= ivData(15 downto 0);
|
| 245 |
|
|
|
| 246 |
|
|
when others =>
|
| 247 |
|
|
svCmd <= ivData(15 downto 0);
|
| 248 |
|
|
end case;
|
| 249 |
|
|
end if;
|
| 250 |
|
|
end if;
|
| 251 |
|
|
end process;
|
| 252 |
3 |
nuxi1209 |
|
| 253 |
2 |
nuxi1209 |
process(iClkReg, iRst_async)
|
| 254 |
|
|
begin
|
| 255 |
|
|
if iRst_async = '1' then
|
| 256 |
|
|
sCmdValid_syncReg_p <= '0';
|
| 257 |
3 |
nuxi1209 |
sCmdStart_syncReg_p <= '0';
|
| 258 |
|
|
elsif rising_edge(iClkReg) then
|
| 259 |
2 |
nuxi1209 |
if iValid_p = '1' and ivAddr = cCMD_ADDR then
|
| 260 |
|
|
sCmdValid_syncReg_p <= '1';
|
| 261 |
|
|
else
|
| 262 |
|
|
sCmdValid_syncReg_p <= '0';
|
| 263 |
|
|
end if;
|
| 264 |
|
|
|
| 265 |
|
|
if iValid_p = '1' and ivAddr = cCMD_ADDR and ivData(15 downto 0) = cCMD_START then
|
| 266 |
|
|
sCmdStart_syncReg_p <= '1';
|
| 267 |
|
|
else
|
| 268 |
|
|
sCmdStart_syncReg_p <= '0';
|
| 269 |
|
|
end if;
|
| 270 |
|
|
end if;
|
| 271 |
|
|
end process;
|
| 272 |
|
|
|
| 273 |
|
|
HandShake_inst : HandShake
|
| 274 |
|
|
port map (
|
| 275 |
|
|
iResetSync_Clk => sReset_syncProcess,
|
| 276 |
|
|
iClk => iClkProcess,
|
| 277 |
|
|
|
| 278 |
|
|
iExternalDemand => sCmdStart_syncReg_p,
|
| 279 |
|
|
oInternalDemand => sCmdStart_syncProcess_p,
|
| 280 |
|
|
iInternalClrDemand => sCmdStart_syncProcess_p
|
| 281 |
|
|
);
|
| 282 |
|
|
|
| 283 |
|
|
process(iClkProcess, iRst_async)
|
| 284 |
|
|
begin
|
| 285 |
|
|
if iRst_async = '1' then
|
| 286 |
|
|
sCmdStart_syncProcess_p_1d <= '0';
|
| 287 |
|
|
elsif rising_edge(iClkProcess) then
|
| 288 |
|
|
sCmdStart_syncProcess_p_1d <= sCmdStart_syncProcess_p;
|
| 289 |
|
|
end if;
|
| 290 |
|
|
end process;
|
| 291 |
|
|
|
| 292 |
|
|
process(iClkProcess)
|
| 293 |
|
|
begin
|
| 294 |
|
|
if rising_edge(iClkProcess) then
|
| 295 |
|
|
if sCmdStart_syncProcess_p = '1' then
|
| 296 |
|
|
for i in 0 to 7 loop
|
| 297 |
|
|
svH(i) <= svMidState(i);
|
| 298 |
|
|
end loop;
|
| 299 |
|
|
|
| 300 |
|
|
svStage1MsgDword(0) <= svMerkleRootDword7;
|
| 301 |
|
|
svStage1MsgDword(1) <= svTimeStamp;
|
| 302 |
|
|
svStage1MsgDword(2) <= svTargetBits;
|
| 303 |
|
|
end if;
|
| 304 |
|
|
end if;
|
| 305 |
|
|
end process;
|
| 306 |
|
|
|
| 307 |
|
|
process(iClkProcess)
|
| 308 |
|
|
begin
|
| 309 |
|
|
if rising_edge(iClkProcess) then
|
| 310 |
|
|
if sCmdStart_syncProcess_p = '1' then
|
| 311 |
|
|
svNonce <= svStartNonce;
|
| 312 |
|
|
elsif sCmdStart_syncProcess_p_1d = '1' or sProcess = stSearch then
|
| 313 |
|
|
svNonce <= svNonce + '1';
|
| 314 |
|
|
end if;
|
| 315 |
|
|
|
| 316 |
|
|
svStage1MsgDword(3) <= svNonce;
|
| 317 |
|
|
end if;
|
| 318 |
|
|
end process;
|
| 319 |
|
|
|
| 320 |
|
|
process(iClkProcess)
|
| 321 |
|
|
begin
|
| 322 |
|
|
if rising_edge(iClkProcess) then
|
| 323 |
|
|
if sCmdStart_syncProcess_p = '1' then
|
| 324 |
|
|
svProcessDelayCnt <= (others=>'0');
|
| 325 |
|
|
sProcessOutValid <= '0';
|
| 326 |
|
|
sProcessOutValid_1d <= '0';
|
| 327 |
|
|
sProcessOutValid_2d <= '0';
|
| 328 |
|
|
else
|
| 329 |
|
|
if sProcess = stSearch and svProcessDelayCnt < cPROCESS_DEALY then
|
| 330 |
|
|
svProcessDelayCnt <= svProcessDelayCnt + '1';
|
| 331 |
|
|
end if;
|
| 332 |
|
|
|
| 333 |
|
|
if sProcess = stSearch and svProcessDelayCnt = cPROCESS_DEALY then
|
| 334 |
|
|
sProcessOutValid <= '1';
|
| 335 |
|
|
elsif sReachEndToIdle = '1' or sFoundNonceToIdle = '1' then
|
| 336 |
|
|
sProcessOutValid <= '0';
|
| 337 |
|
|
end if;
|
| 338 |
|
|
|
| 339 |
|
|
sProcessOutValid_1d <= sProcessOutValid;
|
| 340 |
|
|
sProcessOutValid_2d <= sProcessOutValid_1d;
|
| 341 |
|
|
end if;
|
| 342 |
|
|
end if;
|
| 343 |
|
|
end process;
|
| 344 |
|
|
|
| 345 |
|
|
process(iClkProcess)
|
| 346 |
|
|
begin
|
| 347 |
|
|
if rising_edge(iClkProcess) then
|
| 348 |
|
|
if sCmdStart_syncProcess_p = '1' then
|
| 349 |
|
|
sProcess <= stIdle;
|
| 350 |
|
|
else
|
| 351 |
|
|
case sProcess is
|
| 352 |
|
|
when stIdle =>
|
| 353 |
|
|
if sCmdStart_syncProcess_p_1d = '1' then
|
| 354 |
|
|
sProcess <= stSearch;
|
| 355 |
|
|
end if;
|
| 356 |
|
|
|
| 357 |
|
|
when stSearch =>
|
| 358 |
|
|
if sFoundNonceToIdle = '1' then
|
| 359 |
|
|
sProcess <= stIdle;
|
| 360 |
|
|
elsif sReachEndToIdle = '1' then
|
| 361 |
|
|
sProcess <= stIdle;
|
| 362 |
|
|
end if;
|
| 363 |
|
|
|
| 364 |
|
|
when others =>
|
| 365 |
|
|
sProcess <= stIdle;
|
| 366 |
|
|
end case;
|
| 367 |
|
|
end if;
|
| 368 |
|
|
end if;
|
| 369 |
|
|
end process;
|
| 370 |
|
|
|
| 371 |
|
|
svStage1MsgDword(4) <= X"80000000";
|
| 372 |
|
|
svStage1MsgDword(5) <= X"00000000";
|
| 373 |
|
|
svStage1MsgDword(6) <= X"00000000";
|
| 374 |
|
|
svStage1MsgDword(7) <= X"00000000";
|
| 375 |
|
|
svStage1MsgDword(8) <= X"00000000";
|
| 376 |
|
|
svStage1MsgDword(9) <= X"00000000";
|
| 377 |
|
|
svStage1MsgDword(10) <= X"00000000";
|
| 378 |
|
|
svStage1MsgDword(11) <= X"00000000";
|
| 379 |
|
|
svStage1MsgDword(12) <= X"00000000";
|
| 380 |
|
|
svStage1MsgDword(13) <= X"00000000";
|
| 381 |
|
|
svStage1MsgDword(14) <= X"00000000";
|
| 382 |
|
|
svStage1MsgDword(15) <= X"00000280";
|
| 383 |
|
|
|
| 384 |
|
|
sha_256_chunk_inst_stage1: sha_256_chunk
|
| 385 |
|
|
generic map(
|
| 386 |
|
|
gMSG_IS_CONSTANT => (3 => '0', others => '1'),
|
| 387 |
|
|
gH_IS_CONST => (others => '1'),
|
| 388 |
|
|
gBASE_DELAY => gBASE_DELAY
|
| 389 |
|
|
)
|
| 390 |
|
|
port map(
|
| 391 |
|
|
iClk => iClkProcess,
|
| 392 |
|
|
iRst_async => iRst_async,
|
| 393 |
|
|
|
| 394 |
|
|
iValid => '0',
|
| 395 |
|
|
|
| 396 |
|
|
ivMsgDword => svStage1MsgDword,
|
| 397 |
|
|
|
| 398 |
|
|
ivH0 => svH(0),
|
| 399 |
|
|
ivH1 => svH(1),
|
| 400 |
|
|
ivH2 => svH(2),
|
| 401 |
|
|
ivH3 => svH(3),
|
| 402 |
|
|
ivH4 => svH(4),
|
| 403 |
|
|
ivH5 => svH(5),
|
| 404 |
|
|
ivH6 => svH(6),
|
| 405 |
|
|
ivH7 => svH(7),
|
| 406 |
|
|
|
| 407 |
|
|
ovH0 => svStage1Digest(0),
|
| 408 |
|
|
ovH1 => svStage1Digest(1),
|
| 409 |
|
|
ovH2 => svStage1Digest(2),
|
| 410 |
|
|
ovH3 => svStage1Digest(3),
|
| 411 |
|
|
ovH4 => svStage1Digest(4),
|
| 412 |
|
|
ovH5 => svStage1Digest(5),
|
| 413 |
|
|
ovH6 => svStage1Digest(6),
|
| 414 |
|
|
ovH7 => svStage1Digest(7),
|
| 415 |
|
|
|
| 416 |
|
|
oValid => open
|
| 417 |
|
|
);
|
| 418 |
|
|
|
| 419 |
|
|
svStage2MsgDword(0) <= svStage1Digest(0);
|
| 420 |
|
|
svStage2MsgDword(1) <= svStage1Digest(1);
|
| 421 |
|
|
svStage2MsgDword(2) <= svStage1Digest(2);
|
| 422 |
|
|
svStage2MsgDword(3) <= svStage1Digest(3);
|
| 423 |
|
|
svStage2MsgDword(4) <= svStage1Digest(4);
|
| 424 |
|
|
svStage2MsgDword(5) <= svStage1Digest(5);
|
| 425 |
|
|
svStage2MsgDword(6) <= svStage1Digest(6);
|
| 426 |
|
|
svStage2MsgDword(7) <= svStage1Digest(7);
|
| 427 |
|
|
svStage2MsgDword(8) <= X"80000000";
|
| 428 |
|
|
svStage2MsgDword(9) <= X"00000000";
|
| 429 |
|
|
svStage2MsgDword(10) <= X"00000000";
|
| 430 |
|
|
svStage2MsgDword(11) <= X"00000000";
|
| 431 |
|
|
svStage2MsgDword(12) <= X"00000000";
|
| 432 |
|
|
svStage2MsgDword(13) <= X"00000000";
|
| 433 |
|
|
svStage2MsgDword(14) <= X"00000000";
|
| 434 |
|
|
svStage2MsgDword(15) <= X"00000100";
|
| 435 |
|
|
|
| 436 |
|
|
sha_256_chunk_inst_stage2: sha_256_chunk
|
| 437 |
|
|
generic map(
|
| 438 |
|
|
gMSG_IS_CONSTANT => (0 => '0',
|
| 439 |
|
|
1 => '0',
|
| 440 |
|
|
2 => '0',
|
| 441 |
|
|
3 => '0',
|
| 442 |
|
|
4 => '0',
|
| 443 |
|
|
5 => '0',
|
| 444 |
|
|
6 => '0',
|
| 445 |
|
|
7 => '0',
|
| 446 |
|
|
others => '1'),
|
| 447 |
|
|
gH_IS_CONST => (others => '1'),
|
| 448 |
|
|
gBASE_DELAY => gBASE_DELAY
|
| 449 |
|
|
)
|
| 450 |
|
|
port map(
|
| 451 |
|
|
iClk => iClkProcess,
|
| 452 |
|
|
iRst_async => iRst_async,
|
| 453 |
|
|
|
| 454 |
|
|
iValid => '0',
|
| 455 |
|
|
|
| 456 |
|
|
ivMsgDword => svStage2MsgDword,
|
| 457 |
|
|
|
| 458 |
|
|
ivH0 => X"6a09e667",
|
| 459 |
|
|
ivH1 => X"bb67ae85",
|
| 460 |
|
|
ivH2 => X"3c6ef372",
|
| 461 |
|
|
ivH3 => X"a54ff53a",
|
| 462 |
|
|
ivH4 => X"510e527f",
|
| 463 |
|
|
ivH5 => X"9b05688c",
|
| 464 |
|
|
ivH6 => X"1f83d9ab",
|
| 465 |
|
|
ivH7 => X"5be0cd19",
|
| 466 |
|
|
|
| 467 |
|
|
ovH0 => svStage2DigestBig(((7 + 1) * 32 - 1) downto (7 * 32)),
|
| 468 |
|
|
ovH1 => svStage2DigestBig(((6 + 1) * 32 - 1) downto (6 * 32)),
|
| 469 |
|
|
ovH2 => svStage2DigestBig(((5 + 1) * 32 - 1) downto (5 * 32)),
|
| 470 |
|
|
ovH3 => svStage2DigestBig(((4 + 1) * 32 - 1) downto (4 * 32)),
|
| 471 |
|
|
ovH4 => svStage2DigestBig(((3 + 1) * 32 - 1) downto (3 * 32)),
|
| 472 |
|
|
ovH5 => svStage2DigestBig(((2 + 1) * 32 - 1) downto (2 * 32)),
|
| 473 |
|
|
ovH6 => svStage2DigestBig(((1 + 1) * 32 - 1) downto (1 * 32)),
|
| 474 |
|
|
ovH7 => svStage2DigestBig(((0 + 1) * 32 - 1) downto (0 * 32)),
|
| 475 |
|
|
|
| 476 |
|
|
oValid => open
|
| 477 |
|
|
);
|
| 478 |
|
|
|
| 479 |
|
|
Stage2DigestLittle_gen : for i in 0 to 31 generate
|
| 480 |
|
|
svStage2DigestLittle(((i + 1) * 8 - 1) downto (i * 8)) <= svStage2DigestBig(((31 - i + 1) * 8 - 1) downto ((31 - i) * 8));
|
| 481 |
|
|
end generate;
|
| 482 |
|
|
|
| 483 |
|
|
Digest_gen : for i in 0 to 7 generate
|
| 484 |
|
|
ovDigest(i) <= svStage2DigestBig(((i + 1) * 32 - 1) downto (i * 32));
|
| 485 |
|
|
end generate;
|
| 486 |
|
|
|
| 487 |
|
|
process(iClkProcess)
|
| 488 |
|
|
begin
|
| 489 |
|
|
if rising_edge(iClkProcess) then
|
| 490 |
|
|
for i in 0 to 31 loop
|
| 491 |
|
|
if svStage2DigestLittle(((i + 1) * 8 - 1) downto (i * 8)) = X"00" then
|
| 492 |
|
|
svDigestIsZero(i) <= '1';
|
| 493 |
|
|
else
|
| 494 |
|
|
svDigestIsZero(i) <= '0';
|
| 495 |
|
|
end if;
|
| 496 |
|
|
end loop;
|
| 497 |
|
|
|
| 498 |
|
|
case svTargetIndex(4 downto 0) is
|
| 499 |
|
|
when "00011" =>
|
| 500 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 3 - 1 downto 8 * (3 - 3));
|
| 501 |
|
|
|
| 502 |
|
|
when "00100" =>
|
| 503 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 4 - 1 downto 8 * (4 - 3));
|
| 504 |
|
|
|
| 505 |
|
|
when "00101" =>
|
| 506 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 5 - 1 downto 8 * (5 - 3));
|
| 507 |
|
|
|
| 508 |
|
|
when "00110" =>
|
| 509 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 6 - 1 downto 8 * (6 - 3));
|
| 510 |
|
|
|
| 511 |
|
|
when "00111" =>
|
| 512 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 7 - 1 downto 8 * (7 - 3));
|
| 513 |
|
|
|
| 514 |
|
|
when "01000" =>
|
| 515 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 8 - 1 downto 8 * (8 - 3));
|
| 516 |
|
|
|
| 517 |
|
|
when "01001" =>
|
| 518 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 9 - 1 downto 8 * (9 - 3));
|
| 519 |
|
|
|
| 520 |
|
|
when "01010" =>
|
| 521 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 10 - 1 downto 8 * (10 - 3));
|
| 522 |
|
|
|
| 523 |
|
|
when "01011" =>
|
| 524 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 11 - 1 downto 8 * (11 - 3));
|
| 525 |
|
|
|
| 526 |
|
|
when "01100" =>
|
| 527 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 12 - 1 downto 8 * (12 - 3));
|
| 528 |
|
|
|
| 529 |
|
|
when "01101" =>
|
| 530 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 13 - 1 downto 8 * (13 - 3));
|
| 531 |
|
|
|
| 532 |
|
|
when "01110" =>
|
| 533 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 14 - 1 downto 8 * (14 - 3));
|
| 534 |
|
|
|
| 535 |
|
|
when "01111" =>
|
| 536 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 15 - 1 downto 8 * (15 - 3));
|
| 537 |
|
|
|
| 538 |
|
|
when "10000" =>
|
| 539 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 16 - 1 downto 8 * (16 - 3));
|
| 540 |
|
|
|
| 541 |
|
|
when "10001" =>
|
| 542 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 17 - 1 downto 8 * (17 - 3));
|
| 543 |
|
|
|
| 544 |
|
|
when "10010" =>
|
| 545 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 18 - 1 downto 8 * (18 - 3));
|
| 546 |
|
|
|
| 547 |
|
|
when "10011" =>
|
| 548 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 19 - 1 downto 8 * (19 - 3));
|
| 549 |
|
|
|
| 550 |
|
|
when "10100" =>
|
| 551 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 20 - 1 downto 8 * (20 - 3));
|
| 552 |
|
|
|
| 553 |
|
|
when "10101" =>
|
| 554 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 21 - 1 downto 8 * (21 - 3));
|
| 555 |
|
|
|
| 556 |
|
|
when "10110" =>
|
| 557 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 22 - 1 downto 8 * (22 - 3));
|
| 558 |
|
|
|
| 559 |
|
|
when "10111" =>
|
| 560 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 23 - 1 downto 8 * (23 - 3));
|
| 561 |
|
|
|
| 562 |
|
|
when "11000" =>
|
| 563 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 24 - 1 downto 8 * (24 - 3));
|
| 564 |
|
|
|
| 565 |
|
|
when "11001" =>
|
| 566 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 25 - 1 downto 8 * (25 - 3));
|
| 567 |
|
|
|
| 568 |
|
|
when "11010" =>
|
| 569 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 26 - 1 downto 8 * (26 - 3));
|
| 570 |
|
|
|
| 571 |
|
|
when "11011" =>
|
| 572 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 27 - 1 downto 8 * (27 - 3));
|
| 573 |
|
|
|
| 574 |
|
|
when "11100" =>
|
| 575 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 28 - 1 downto 8 * (28 - 3));
|
| 576 |
|
|
|
| 577 |
|
|
when others => --"11101", Maximum difficulty
|
| 578 |
|
|
svDigestSignificant <= svStage2DigestLittle(8 * 29 - 1 downto 8 * (29 - 3));
|
| 579 |
|
|
end case;
|
| 580 |
|
|
end if;
|
| 581 |
|
|
end process;
|
| 582 |
|
|
|
| 583 |
|
|
svTargetIndex <= svTargetBits(7 downto 0);
|
| 584 |
|
|
svTargetFraction(7 downto 0) <= svTargetBits(31 downto 24);
|
| 585 |
|
|
svTargetFraction(15 downto 8) <= svTargetBits(23 downto 16);
|
| 586 |
|
|
svTargetFraction(23 downto 16) <= svTargetBits(15 downto 8);
|
| 587 |
|
|
|
| 588 |
|
|
process(iClkProcess)
|
| 589 |
|
|
begin
|
| 590 |
|
|
if rising_edge(iClkProcess) then
|
| 591 |
|
|
case svTargetIndex(4 downto 0) is
|
| 592 |
|
|
when "00011" =>
|
| 593 |
|
|
if svDigestIsZero(31 downto 3) = conv_std_logic_vector(-1, 31 - 3 + 1) then
|
| 594 |
|
|
sDigestHighBitsZero <= '1';
|
| 595 |
|
|
else
|
| 596 |
|
|
sDigestHighBitsZero <= '0';
|
| 597 |
|
|
end if;
|
| 598 |
|
|
|
| 599 |
|
|
when "00100" =>
|
| 600 |
|
|
if svDigestIsZero(31 downto 4) = conv_std_logic_vector(-1, 31 - 4 + 1) then
|
| 601 |
|
|
sDigestHighBitsZero <= '1';
|
| 602 |
|
|
else
|
| 603 |
|
|
sDigestHighBitsZero <= '0';
|
| 604 |
|
|
end if;
|
| 605 |
|
|
|
| 606 |
|
|
when "00101" =>
|
| 607 |
|
|
if svDigestIsZero(31 downto 5) = conv_std_logic_vector(-1, 31 - 5 + 1) then
|
| 608 |
|
|
sDigestHighBitsZero <= '1';
|
| 609 |
|
|
else
|
| 610 |
|
|
sDigestHighBitsZero <= '0';
|
| 611 |
|
|
end if;
|
| 612 |
|
|
|
| 613 |
|
|
when "00110" =>
|
| 614 |
|
|
if svDigestIsZero(31 downto 6) = conv_std_logic_vector(-1, 31 - 6 + 1) then
|
| 615 |
|
|
sDigestHighBitsZero <= '1';
|
| 616 |
|
|
else
|
| 617 |
|
|
sDigestHighBitsZero <= '0';
|
| 618 |
|
|
end if;
|
| 619 |
|
|
|
| 620 |
|
|
when "00111" =>
|
| 621 |
|
|
if svDigestIsZero(31 downto 7) = conv_std_logic_vector(-1, 31 - 7 + 1) then
|
| 622 |
|
|
sDigestHighBitsZero <= '1';
|
| 623 |
|
|
else
|
| 624 |
|
|
sDigestHighBitsZero <= '0';
|
| 625 |
|
|
end if;
|
| 626 |
|
|
|
| 627 |
|
|
when "01000" =>
|
| 628 |
|
|
if svDigestIsZero(31 downto 8) = conv_std_logic_vector(-1, 31 - 8 + 1) then
|
| 629 |
|
|
sDigestHighBitsZero <= '1';
|
| 630 |
|
|
else
|
| 631 |
|
|
sDigestHighBitsZero <= '0';
|
| 632 |
|
|
end if;
|
| 633 |
|
|
|
| 634 |
|
|
when "01001" =>
|
| 635 |
|
|
if svDigestIsZero(31 downto 9) = conv_std_logic_vector(-1, 31 - 9 + 1) then
|
| 636 |
|
|
sDigestHighBitsZero <= '1';
|
| 637 |
|
|
else
|
| 638 |
|
|
sDigestHighBitsZero <= '0';
|
| 639 |
|
|
end if;
|
| 640 |
|
|
|
| 641 |
|
|
when "01010" =>
|
| 642 |
|
|
if svDigestIsZero(31 downto 10) = conv_std_logic_vector(-1, 31 - 10 + 1) then
|
| 643 |
|
|
sDigestHighBitsZero <= '1';
|
| 644 |
|
|
else
|
| 645 |
|
|
sDigestHighBitsZero <= '0';
|
| 646 |
|
|
end if;
|
| 647 |
|
|
|
| 648 |
|
|
when "01011" =>
|
| 649 |
|
|
if svDigestIsZero(31 downto 11) = conv_std_logic_vector(-1, 31 - 11 + 1) then
|
| 650 |
|
|
sDigestHighBitsZero <= '1';
|
| 651 |
|
|
else
|
| 652 |
|
|
sDigestHighBitsZero <= '0';
|
| 653 |
|
|
end if;
|
| 654 |
|
|
|
| 655 |
|
|
when "01100" =>
|
| 656 |
|
|
if svDigestIsZero(31 downto 12) = conv_std_logic_vector(-1, 31 - 12 + 1) then
|
| 657 |
|
|
sDigestHighBitsZero <= '1';
|
| 658 |
|
|
else
|
| 659 |
|
|
sDigestHighBitsZero <= '0';
|
| 660 |
|
|
end if;
|
| 661 |
|
|
|
| 662 |
|
|
when "01101" =>
|
| 663 |
|
|
if svDigestIsZero(31 downto 13) = conv_std_logic_vector(-1, 31 -13 + 1) then
|
| 664 |
|
|
sDigestHighBitsZero <= '1';
|
| 665 |
|
|
else
|
| 666 |
|
|
sDigestHighBitsZero <= '0';
|
| 667 |
|
|
end if;
|
| 668 |
|
|
|
| 669 |
|
|
when "01110" =>
|
| 670 |
|
|
if svDigestIsZero(31 downto 14) = conv_std_logic_vector(-1, 31 - 14 + 1) then
|
| 671 |
|
|
sDigestHighBitsZero <= '1';
|
| 672 |
|
|
else
|
| 673 |
|
|
sDigestHighBitsZero <= '0';
|
| 674 |
|
|
end if;
|
| 675 |
|
|
|
| 676 |
|
|
when "01111" =>
|
| 677 |
|
|
if svDigestIsZero(31 downto 15) = conv_std_logic_vector(-1, 31 - 15 + 1) then
|
| 678 |
|
|
sDigestHighBitsZero <= '1';
|
| 679 |
|
|
else
|
| 680 |
|
|
sDigestHighBitsZero <= '0';
|
| 681 |
|
|
end if;
|
| 682 |
|
|
|
| 683 |
|
|
when "10000" =>
|
| 684 |
|
|
if svDigestIsZero(31 downto 16) = conv_std_logic_vector(-1, 31 - 16 + 1) then
|
| 685 |
|
|
sDigestHighBitsZero <= '1';
|
| 686 |
|
|
else
|
| 687 |
|
|
sDigestHighBitsZero <= '0';
|
| 688 |
|
|
end if;
|
| 689 |
|
|
|
| 690 |
|
|
when "10001" =>
|
| 691 |
|
|
if svDigestIsZero(31 downto 17) = conv_std_logic_vector(-1, 31 - 17 + 1) then
|
| 692 |
|
|
sDigestHighBitsZero <= '1';
|
| 693 |
|
|
else
|
| 694 |
|
|
sDigestHighBitsZero <= '0';
|
| 695 |
|
|
end if;
|
| 696 |
|
|
|
| 697 |
|
|
when "10010" =>
|
| 698 |
|
|
if svDigestIsZero(31 downto 18) = conv_std_logic_vector(-1, 31 - 18 + 1) then
|
| 699 |
|
|
sDigestHighBitsZero <= '1';
|
| 700 |
|
|
else
|
| 701 |
|
|
sDigestHighBitsZero <= '0';
|
| 702 |
|
|
end if;
|
| 703 |
|
|
|
| 704 |
|
|
when "10011" =>
|
| 705 |
|
|
if svDigestIsZero(31 downto 19) = conv_std_logic_vector(-1, 31 - 19 + 1) then
|
| 706 |
|
|
sDigestHighBitsZero <= '1';
|
| 707 |
|
|
else
|
| 708 |
|
|
sDigestHighBitsZero <= '0';
|
| 709 |
|
|
end if;
|
| 710 |
|
|
|
| 711 |
|
|
when "10100" =>
|
| 712 |
|
|
if svDigestIsZero(31 downto 20) = conv_std_logic_vector(-1, 31 - 20 + 1) then
|
| 713 |
|
|
sDigestHighBitsZero <= '1';
|
| 714 |
|
|
else
|
| 715 |
|
|
sDigestHighBitsZero <= '0';
|
| 716 |
|
|
end if;
|
| 717 |
|
|
|
| 718 |
|
|
when "10101" =>
|
| 719 |
|
|
if svDigestIsZero(31 downto 21) = conv_std_logic_vector(-1, 31 - 21 + 1) then
|
| 720 |
|
|
sDigestHighBitsZero <= '1';
|
| 721 |
|
|
else
|
| 722 |
|
|
sDigestHighBitsZero <= '0';
|
| 723 |
|
|
end if;
|
| 724 |
|
|
|
| 725 |
|
|
when "10110" =>
|
| 726 |
|
|
if svDigestIsZero(31 downto 22) = conv_std_logic_vector(-1, 31 - 22 + 1) then
|
| 727 |
|
|
sDigestHighBitsZero <= '1';
|
| 728 |
|
|
else
|
| 729 |
|
|
sDigestHighBitsZero <= '0';
|
| 730 |
|
|
end if;
|
| 731 |
|
|
|
| 732 |
|
|
when "10111" =>
|
| 733 |
|
|
if svDigestIsZero(31 downto 23) = conv_std_logic_vector(-1, 31 - 23 + 1) then
|
| 734 |
|
|
sDigestHighBitsZero <= '1';
|
| 735 |
|
|
else
|
| 736 |
|
|
sDigestHighBitsZero <= '0';
|
| 737 |
|
|
end if;
|
| 738 |
|
|
|
| 739 |
|
|
when "11000" =>
|
| 740 |
|
|
if svDigestIsZero(31 downto 24) = conv_std_logic_vector(-1, 31 - 24 + 1) then
|
| 741 |
|
|
sDigestHighBitsZero <= '1';
|
| 742 |
|
|
else
|
| 743 |
|
|
sDigestHighBitsZero <= '0';
|
| 744 |
|
|
end if;
|
| 745 |
|
|
|
| 746 |
|
|
when "11001" =>
|
| 747 |
|
|
if svDigestIsZero(31 downto 25) = conv_std_logic_vector(-1, 31 - 25 + 1) then
|
| 748 |
|
|
sDigestHighBitsZero <= '1';
|
| 749 |
|
|
else
|
| 750 |
|
|
sDigestHighBitsZero <= '0';
|
| 751 |
|
|
end if;
|
| 752 |
|
|
|
| 753 |
|
|
when "11010" =>
|
| 754 |
|
|
if svDigestIsZero(31 downto 26) = conv_std_logic_vector(-1, 31 - 26 + 1) then
|
| 755 |
|
|
sDigestHighBitsZero <= '1';
|
| 756 |
|
|
else
|
| 757 |
|
|
sDigestHighBitsZero <= '0';
|
| 758 |
|
|
end if;
|
| 759 |
|
|
|
| 760 |
|
|
when "11011" =>
|
| 761 |
|
|
if svDigestIsZero(31 downto 27) = conv_std_logic_vector(-1, 31 - 27 + 1) then
|
| 762 |
|
|
sDigestHighBitsZero <= '1';
|
| 763 |
|
|
else
|
| 764 |
|
|
sDigestHighBitsZero <= '0';
|
| 765 |
|
|
end if;
|
| 766 |
|
|
|
| 767 |
|
|
when "11100" =>
|
| 768 |
|
|
if svDigestIsZero(31 downto 28) = conv_std_logic_vector(-1, 31 - 28 + 1) then
|
| 769 |
|
|
sDigestHighBitsZero <= '1';
|
| 770 |
|
|
else
|
| 771 |
|
|
sDigestHighBitsZero <= '0';
|
| 772 |
|
|
end if;
|
| 773 |
|
|
|
| 774 |
|
|
when others => --"11101", Maximum difficulty
|
| 775 |
|
|
if svDigestIsZero(31 downto 29) = conv_std_logic_vector(-1, 31 - 29 + 1) then
|
| 776 |
|
|
sDigestHighBitsZero <= '1';
|
| 777 |
|
|
else
|
| 778 |
|
|
sDigestHighBitsZero <= '0';
|
| 779 |
|
|
end if;
|
| 780 |
|
|
end case;
|
| 781 |
|
|
|
| 782 |
|
|
if svDigestSignificant <= svTargetFraction(23 downto 0) then
|
| 783 |
|
|
sDigestSignificantFit <= '1';
|
| 784 |
|
|
else
|
| 785 |
|
|
sDigestSignificantFit <= '0';
|
| 786 |
|
|
end if;
|
| 787 |
|
|
end if;
|
| 788 |
|
|
end process;
|
| 789 |
|
|
|
| 790 |
|
|
process(iClkProcess)
|
| 791 |
|
|
begin
|
| 792 |
|
|
if rising_edge(iClkProcess) then
|
| 793 |
|
|
if sCmdStart_syncProcess_p = '1' then
|
| 794 |
|
|
svCmpDelayCnt <= (others=>'0');
|
| 795 |
|
|
sCmpResultValid <= '0';
|
| 796 |
|
|
else
|
| 797 |
|
|
if sProcess = stSearch and svCmpDelayCnt < cCMP_DELAY then
|
| 798 |
|
|
svCmpDelayCnt <= svCmpDelayCnt + '1';
|
| 799 |
|
|
end if;
|
| 800 |
|
|
|
| 801 |
|
|
if sProcess = stSearch and svCmpDelayCnt = cCMP_DELAY then
|
| 802 |
|
|
sCmpResultValid <= '1';
|
| 803 |
|
|
else
|
| 804 |
|
|
sCmpResultValid <= '0';
|
| 805 |
|
|
end if;
|
| 806 |
|
|
end if;
|
| 807 |
|
|
end if;
|
| 808 |
|
|
end process;
|
| 809 |
|
|
|
| 810 |
|
|
process(iClkProcess)
|
| 811 |
|
|
begin
|
| 812 |
|
|
if rising_edge(iClkProcess) then
|
| 813 |
|
|
if sCmdStart_syncProcess_p = '1' then
|
| 814 |
|
|
svCmpNounce <= svStartNonce;
|
| 815 |
|
|
elsif sCmpResultValid = '1' then
|
| 816 |
|
|
svCmpNounce <= svCmpNounce + '1';
|
| 817 |
|
|
end if;
|
| 818 |
|
|
end if;
|
| 819 |
|
|
end process;
|
| 820 |
|
|
|
| 821 |
|
|
process(iClkProcess)
|
| 822 |
|
|
begin
|
| 823 |
|
|
if rising_edge(iClkProcess) then
|
| 824 |
|
|
if sCmdStart_syncProcess_p = '1' then
|
| 825 |
|
|
sReachEndToIdle <= '0';
|
| 826 |
|
|
else
|
| 827 |
|
|
if sProcess = stSearch and sCmpResultValid = '1' and svCmpNounce = svEndNonce then
|
| 828 |
|
|
sReachEndToIdle <= '1';
|
| 829 |
|
|
else
|
| 830 |
|
|
sReachEndToIdle <= '0';
|
| 831 |
|
|
end if;
|
| 832 |
|
|
end if;
|
| 833 |
|
|
end if;
|
| 834 |
|
|
end process;
|
| 835 |
|
|
|
| 836 |
|
|
process(iClkProcess)
|
| 837 |
|
|
begin
|
| 838 |
|
|
if rising_edge(iClkProcess) then
|
| 839 |
|
|
if sCmdStart_syncProcess_p = '1' then
|
| 840 |
|
|
oReachEnd <= '0';
|
| 841 |
|
|
else
|
| 842 |
|
|
if sProcess = stSearch and sReachEndToIdle = '1' and sFoundNonceToIdle = '0' then
|
| 843 |
|
|
oReachEnd <= '1';
|
| 844 |
|
|
else
|
| 845 |
|
|
oReachEnd <= '0';
|
| 846 |
|
|
end if;
|
| 847 |
|
|
end if;
|
| 848 |
|
|
end if;
|
| 849 |
|
|
end process;
|
| 850 |
|
|
|
| 851 |
|
|
process(iClkProcess)
|
| 852 |
|
|
begin
|
| 853 |
|
|
if rising_edge(iClkProcess) then
|
| 854 |
|
|
if sCmdStart_syncProcess_p = '1' then
|
| 855 |
|
|
sFoundNonceToIdle <= '0';
|
| 856 |
|
|
else
|
| 857 |
|
|
if sProcess = stSearch and sCmpResultValid = '1' and sDigestHighBitsZero = '1' and sDigestSignificantFit = '1' then
|
| 858 |
|
|
sFoundNonceToIdle <= '1';
|
| 859 |
|
|
else
|
| 860 |
|
|
sFoundNonceToIdle <= '0';
|
| 861 |
|
|
end if;
|
| 862 |
|
|
end if;
|
| 863 |
|
|
end if;
|
| 864 |
|
|
end process;
|
| 865 |
|
|
|
| 866 |
|
|
process(iClkProcess)
|
| 867 |
|
|
begin
|
| 868 |
|
|
if rising_edge(iClkProcess) then
|
| 869 |
|
|
if sCmdStart_syncProcess_p = '1' then
|
| 870 |
|
|
oFoundNonce <= '0';
|
| 871 |
|
|
else
|
| 872 |
|
|
if sProcess = stSearch and sFoundNonceToIdle = '1' then
|
| 873 |
|
|
oFoundNonce <= '1';
|
| 874 |
|
|
else
|
| 875 |
|
|
oFoundNonce <= '0';
|
| 876 |
|
|
end if;
|
| 877 |
|
|
end if;
|
| 878 |
|
|
end if;
|
| 879 |
|
|
end process;
|
| 880 |
|
|
|
| 881 |
|
|
pipelines_without_reset_inst_Nonce : pipelines_without_reset
|
| 882 |
|
|
GENERIC map(gBUS_WIDTH => 32, gNB_PIPELINES => 2)
|
| 883 |
|
|
PORT map(
|
| 884 |
|
|
iClk => iClkProcess,
|
| 885 |
|
|
iInput => '0',
|
| 886 |
|
|
ivInput => svCmpNounce,
|
| 887 |
|
|
oDelayed_output => open,
|
| 888 |
|
|
ovDelayed_output => ovNonce
|
| 889 |
|
|
);
|
| 890 |
|
|
|
| 891 |
|
|
end behavioral;
|
