Subversion Repositories btc_dsha256

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--                                                               --

--  Copyright (C) 2013 Author and VariStream Studio              --

--  Author : Yu Peng                                             --

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--  This source file may be used and distributed without         -- 

--  restriction provided that this copyright statement is not    -- 

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--  This source file is free software; you can redistribute it   -- 

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--  You should have received a copy of the GNU Lesser General    -- 

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--  Notes : Introduce delay of 1 clock cycle

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use ieee.std_logic_unsigned.all;

use work.sha_256_pkg.ALL;

entity sha_256_ext_func_1c is

        port(

                iClk : in std_logic;

                iRst_async : in std_logic;

                ivWIM2 : in std_logic_vector(31 downto 0);

                ivWIM7 : in std_logic_vector(31 downto 0);

                ivWIM15 : in std_logic_vector(31 downto 0);

                ivWIM16 : in std_logic_vector(31 downto 0);

                ovWO : out std_logic_vector(31 downto 0)

        );

end sha_256_ext_func_1c;

architecture behavioral of sha_256_ext_func_1c is

begin

        process(iClk)

        begin

                if rising_edge(iClk) then

                        ovWO <= ivWIM16 + sigma_0(ivWIM15) + ivWIM7 + sigma_1(ivWIM2);

                end if;

        end process;

end behavioral;