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ash_riple |
############################################################################
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##
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## Xilinx, Inc. 2006 www.xilinx.com
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############################################################################
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## File name : data/ps7_constraints.ucf
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##
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## Details : Constraints file
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## FPGA family: zynq
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## FPGA: xc7z020clg484-1
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## Device Size: xc7z020
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## Package: clg484
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## Speedgrade: -1
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##
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##Note: This is a generated file. Configuration settings should not be edited
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##
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############################################################################
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############################################################################
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############################################################################
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# I/O STANDARDS and Location Constraints #
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############################################################################
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NET "MIO[53]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "C12" | PULLUP = "TRUE" ; # Enet 0 / mdio / MIO[53]
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NET "MIO[52]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "D10" | PULLUP = "TRUE" ; # Enet 0 / mdc / MIO[52]
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NET "MIO[51]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "C10" | PULLUP = "TRUE" ; # I2C 0 / sda / MIO[51]
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NET "MIO[50]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "D13" | PULLUP = "TRUE" ; # I2C 0 / scl / MIO[50]
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NET "MIO[49]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "C14" | PULLUP = "TRUE" ; # UART 1 / rx / MIO[49]
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NET "MIO[48]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "D11" | PULLUP = "TRUE" ; # UART 1 / tx / MIO[48]
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NET "MIO[47]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "B10" | PULLUP = "TRUE" ; # CAN 0 / tx / MIO[47]
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NET "MIO[46]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "D12" | PULLUP = "TRUE" ; # CAN 0 / rx / MIO[46]
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NET "MIO[45]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "B9" | PULLUP = "TRUE" ; # SD 0 / data[3] / MIO[45]
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NET "MIO[44]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "E13" | PULLUP = "TRUE" ; # SD 0 / data[2] / MIO[44]
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NET "MIO[43]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "B11" | PULLUP = "TRUE" ; # SD 0 / data[1] / MIO[43]
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NET "MIO[42]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "D8" | PULLUP = "TRUE" ; # SD 0 / data[0] / MIO[42]
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NET "MIO[41]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "C8" | PULLUP = "TRUE" ; # SD 0 / cmd / MIO[41]
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NET "MIO[40]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "E14" | PULLUP = "TRUE" ; # SD 0 / clk / MIO[40]
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NET "MIO[39]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "C13" | PULLUP = "TRUE" ; # USB 0 / data[7] / MIO[39]
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NET "MIO[38]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "F13" | PULLUP = "TRUE" ; # USB 0 / data[6] / MIO[38]
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NET "MIO[37]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "B14" | PULLUP = "TRUE" ; # USB 0 / data[5] / MIO[37]
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NET "MIO[36]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "A9" | PULLUP = "TRUE" ; # USB 0 / clk / MIO[36]
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NET "MIO[35]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "F14" | PULLUP = "TRUE" ; # USB 0 / data[3] / MIO[35]
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NET "MIO[34]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "B12" | PULLUP = "TRUE" ; # USB 0 / data[2] / MIO[34]
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NET "MIO[33]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "G13" | PULLUP = "TRUE" ; # USB 0 / data[1] / MIO[33]
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NET "MIO[32]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "C7" | PULLUP = "TRUE" ; # USB 0 / data[0] / MIO[32]
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NET "MIO[31]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "F9" | PULLUP = "TRUE" ; # USB 0 / nxt / MIO[31]
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NET "MIO[30]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "A11" | PULLUP = "TRUE" ; # USB 0 / stp / MIO[30]
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NET "MIO[29]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "E8" | PULLUP = "TRUE" ; # USB 0 / dir / MIO[29]
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NET "MIO[28]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "A12" | PULLUP = "TRUE" ; # USB 0 / data[4] / MIO[28]
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NET "MIO[27]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "D7" | PULLUP = "TRUE" ; # Enet 0 / rx_ctl / MIO[27]
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NET "MIO[26]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "A13" | PULLUP = "TRUE" ; # Enet 0 / rxd[3] / MIO[26]
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NET "MIO[25]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "F12" | PULLUP = "TRUE" ; # Enet 0 / rxd[2] / MIO[25]
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NET "MIO[24]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "B7" | PULLUP = "TRUE" ; # Enet 0 / rxd[1] / MIO[24]
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NET "MIO[23]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "E11" | PULLUP = "TRUE" ; # Enet 0 / rxd[0] / MIO[23]
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NET "MIO[22]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "A14" | PULLUP = "TRUE" ; # Enet 0 / rx_clk / MIO[22]
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NET "MIO[21]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "F11" | PULLUP = "TRUE" ; # Enet 0 / tx_ctl / MIO[21]
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NET "MIO[20]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "A8" | PULLUP = "TRUE" ; # Enet 0 / txd[3] / MIO[20]
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NET "MIO[19]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "E10" | PULLUP = "TRUE" ; # Enet 0 / txd[2] / MIO[19]
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NET "MIO[18]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "A7" | PULLUP = "TRUE" ; # Enet 0 / txd[1] / MIO[18]
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NET "MIO[17]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "E9" | PULLUP = "TRUE" ; # Enet 0 / txd[0] / MIO[17]
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NET "MIO[16]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "D6" | PULLUP = "TRUE" ; # Enet 0 / tx_clk / MIO[16]
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NET "MIO[15]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "E6" | PULLUP = "TRUE" ; # SD 0 / wp / MIO[15]
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NET "MIO[14]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "B6" | PULLUP = "TRUE" ; # GPIO / gpio[14] / MIO[14]
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NET "MIO[13]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "A6" | PULLUP = "TRUE" ; # GPIO / gpio[13] / MIO[13]
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NET "MIO[12]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "C5" | PULLUP = "TRUE" ; # GPIO / gpio[12] / MIO[12]
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NET "MIO[11]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "B4" | PULLUP = "TRUE" ; # GPIO / gpio[11] / MIO[11]
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NET "MIO[10]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "G7" | PULLUP = "TRUE" ; # GPIO / gpio[10] / MIO[10]
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NET "MIO[9]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "C4" | PULLUP = "TRUE" ; # GPIO / gpio[9] / MIO[9]
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NET "MIO[8]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "E5" ; # Quad SPI Flash / qspi_fbclk / MIO[8]
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NET "MIO[7]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "D5" ; # GPIO / gpio[7] / MIO[7]
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NET "MIO[6]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "A4" ; # Quad SPI Flash / qspi0_sclk / MIO[6]
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NET "MIO[5]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "A3" ; # Quad SPI Flash / qspi0_io[3] / MIO[5]
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NET "MIO[4]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "E4" ; # Quad SPI Flash / qspi0_io[2] / MIO[4]
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NET "MIO[3]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "F6" ; # Quad SPI Flash / qspi0_io[1] / MIO[3]
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NET "MIO[2]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "A2" ; # Quad SPI Flash / qspi0_io[0] / MIO[2]
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NET "MIO[1]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "A1" | PULLUP = "TRUE" ; # Quad SPI Flash / qspi0_ss_b / MIO[1]
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NET "MIO[0]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "G6" | PULLUP = "TRUE" ; # SD 0 / cd / MIO[0]
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NET "DDR_WEB" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "R4" ;
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NET "DDR_VRP" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "N7" ;
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NET "DDR_VRN" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "M7" ;
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NET "DDR_RAS_n" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "R5" ;
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NET "DDR_ODT" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "P5" ;
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NET "DDR_DRSTB" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "F3" ;
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NET "DDR_DQS[3]" IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "V2" ;
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NET "DDR_DQS[2]" IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "N2" ;
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NET "DDR_DQS[1]" IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "H2" ;
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NET "DDR_DQS[0]" IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "C2" ;
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NET "DDR_DQS_n[3]" IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "W2" ;
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NET "DDR_DQS_n[2]" IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "P2" ;
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NET "DDR_DQS_n[1]" IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "J2" ;
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NET "DDR_DQS_n[0]" IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "D2" ;
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NET "DDR_DQ[9]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "G1" ;
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NET "DDR_DQ[8]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "G2" ;
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NET "DDR_DQ[7]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "F1" ;
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NET "DDR_DQ[6]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "F2" ;
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| 94 |
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NET "DDR_DQ[5]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "E1" ;
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NET "DDR_DQ[4]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "E3" ;
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| 96 |
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NET "DDR_DQ[3]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "D3" ;
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| 97 |
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NET "DDR_DQ[31]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "Y1" ;
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| 98 |
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NET "DDR_DQ[30]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "W3" ;
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| 99 |
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NET "DDR_DQ[2]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "B2" ;
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| 100 |
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NET "DDR_DQ[29]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "Y3" ;
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| 101 |
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NET "DDR_DQ[28]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "W1" ;
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| 102 |
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NET "DDR_DQ[27]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "U2" ;
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| 103 |
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NET "DDR_DQ[26]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "AA1" ;
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| 104 |
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NET "DDR_DQ[25]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "U1" ;
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| 105 |
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NET "DDR_DQ[24]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "AA3" ;
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| 106 |
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NET "DDR_DQ[23]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "R1" ;
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| 107 |
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NET "DDR_DQ[22]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "M2" ;
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| 108 |
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NET "DDR_DQ[21]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "T2" ;
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| 109 |
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NET "DDR_DQ[20]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "R3" ;
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| 110 |
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NET "DDR_DQ[1]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "C3" ;
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| 111 |
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NET "DDR_DQ[19]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "T1" ;
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| 112 |
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NET "DDR_DQ[18]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "N3" ;
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| 113 |
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NET "DDR_DQ[17]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "T3" ;
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| 114 |
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NET "DDR_DQ[16]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "M1" ;
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| 115 |
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NET "DDR_DQ[15]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "K3" ;
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| 116 |
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NET "DDR_DQ[14]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "J1" ;
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| 117 |
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NET "DDR_DQ[13]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "K1" ;
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| 118 |
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NET "DDR_DQ[12]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "L3" ;
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| 119 |
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NET "DDR_DQ[11]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "L2" ;
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| 120 |
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NET "DDR_DQ[10]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "L1" ;
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| 121 |
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NET "DDR_DQ[0]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "D1" ;
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| 122 |
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NET "DDR_DM[3]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "AA2" ;
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| 123 |
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NET "DDR_DM[2]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "P1" ;
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| 124 |
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NET "DDR_DM[1]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "H3" ;
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| 125 |
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NET "DDR_DM[0]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "B1" ;
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| 126 |
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NET "DDR_CS_n" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "P6" ;
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| 127 |
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NET "DDR_CKE" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "V3" ;
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| 128 |
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NET "DDR_Clk" IOSTANDARD = DIFF_SSTL15 | SLEW = "FAST" | LOC = "N4" ;
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| 129 |
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NET "DDR_Clk_n" IOSTANDARD = DIFF_SSTL15 | SLEW = "FAST" | LOC = "N5" ;
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| 130 |
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NET "DDR_CAS_n" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "P3" ;
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| 131 |
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NET "DDR_BankAddr[2]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "M6" ;
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| 132 |
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NET "DDR_BankAddr[1]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "L6" ;
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| 133 |
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NET "DDR_BankAddr[0]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "L7" ;
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| 134 |
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NET "DDR_Addr[9]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "H5" ;
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| 135 |
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NET "DDR_Addr[8]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "J5" ;
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| 136 |
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NET "DDR_Addr[7]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "J6" ;
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| 137 |
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NET "DDR_Addr[6]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "J7" ;
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| 138 |
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NET "DDR_Addr[5]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "K5" ;
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| 139 |
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NET "DDR_Addr[4]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "K6" ;
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| 140 |
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NET "DDR_Addr[3]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "L4" ;
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| 141 |
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NET "DDR_Addr[2]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "K4" ;
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| 142 |
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NET "DDR_Addr[1]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "M5" ;
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| 143 |
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NET "DDR_Addr[14]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "G4" ;
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| 144 |
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NET "DDR_Addr[13]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "F4" ;
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| 145 |
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NET "DDR_Addr[12]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "H4" ;
|
| 146 |
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NET "DDR_Addr[11]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "G5" ;
|
| 147 |
|
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NET "DDR_Addr[10]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "J3" ;
|
| 148 |
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NET "DDR_Addr[0]" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "M4" ;
|
| 149 |
|
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NET "PS_PORB" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "B5" ;
|
| 150 |
|
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NET "PS_SRSTB" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "C9" ;
|
| 151 |
|
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NET "PS_CLK" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "F7" ;
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