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ash_riple |
############################################################################
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##
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## Xilinx, Inc. 2006 www.xilinx.com
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############################################################################
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## File name : data/ps7_constraints.xdc
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##
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## Details : Constraints file
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## FPGA family: zynq
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## FPGA: xc7z020clg484-1
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## Device Size: xc7z020
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## Package: clg484
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## Speedgrade: -1
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##
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##Note: This is a generated file. Configuration settings should not be edited
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##
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############################################################################
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############################################################################
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############################################################################
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# I/O STANDARDS and Location Constraints #
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############################################################################
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# Enet 0 / mdio / MIO[53]
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| 23 |
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set_property iostandard "LVCMOS18" [get_ports "MIO[53]"]
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| 24 |
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set_property PACKAGE_PIN "C12" [get_ports "MIO[53]"]
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| 25 |
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set_property slew "slow" [get_ports "MIO[53]"]
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| 26 |
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set_property drive "8" [get_ports "MIO[53]"]
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| 27 |
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set_property pullup "TRUE" [get_ports "MIO[53]"]
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| 28 |
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# Enet 0 / mdc / MIO[52]
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| 29 |
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set_property iostandard "LVCMOS18" [get_ports "MIO[52]"]
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| 30 |
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set_property PACKAGE_PIN "D10" [get_ports "MIO[52]"]
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| 31 |
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set_property slew "slow" [get_ports "MIO[52]"]
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| 32 |
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set_property drive "8" [get_ports "MIO[52]"]
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| 33 |
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set_property pullup "TRUE" [get_ports "MIO[52]"]
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| 34 |
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# I2C 0 / sda / MIO[51]
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| 35 |
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set_property iostandard "LVCMOS18" [get_ports "MIO[51]"]
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| 36 |
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set_property PACKAGE_PIN "C10" [get_ports "MIO[51]"]
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| 37 |
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set_property slew "slow" [get_ports "MIO[51]"]
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| 38 |
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set_property drive "8" [get_ports "MIO[51]"]
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| 39 |
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set_property pullup "TRUE" [get_ports "MIO[51]"]
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| 40 |
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# I2C 0 / scl / MIO[50]
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| 41 |
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set_property iostandard "LVCMOS18" [get_ports "MIO[50]"]
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| 42 |
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set_property PACKAGE_PIN "D13" [get_ports "MIO[50]"]
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| 43 |
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set_property slew "slow" [get_ports "MIO[50]"]
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| 44 |
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set_property drive "8" [get_ports "MIO[50]"]
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| 45 |
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set_property pullup "TRUE" [get_ports "MIO[50]"]
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| 46 |
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# UART 1 / rx / MIO[49]
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| 47 |
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set_property iostandard "LVCMOS18" [get_ports "MIO[49]"]
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| 48 |
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set_property PACKAGE_PIN "C14" [get_ports "MIO[49]"]
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| 49 |
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set_property slew "slow" [get_ports "MIO[49]"]
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| 50 |
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set_property drive "8" [get_ports "MIO[49]"]
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| 51 |
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set_property pullup "TRUE" [get_ports "MIO[49]"]
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| 52 |
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# UART 1 / tx / MIO[48]
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| 53 |
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set_property iostandard "LVCMOS18" [get_ports "MIO[48]"]
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| 54 |
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set_property PACKAGE_PIN "D11" [get_ports "MIO[48]"]
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| 55 |
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set_property slew "slow" [get_ports "MIO[48]"]
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| 56 |
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set_property drive "8" [get_ports "MIO[48]"]
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| 57 |
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set_property pullup "TRUE" [get_ports "MIO[48]"]
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| 58 |
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# CAN 0 / tx / MIO[47]
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| 59 |
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set_property iostandard "LVCMOS18" [get_ports "MIO[47]"]
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| 60 |
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set_property PACKAGE_PIN "B10" [get_ports "MIO[47]"]
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| 61 |
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set_property slew "slow" [get_ports "MIO[47]"]
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| 62 |
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set_property drive "8" [get_ports "MIO[47]"]
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| 63 |
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set_property pullup "TRUE" [get_ports "MIO[47]"]
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| 64 |
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# CAN 0 / rx / MIO[46]
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| 65 |
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set_property iostandard "LVCMOS18" [get_ports "MIO[46]"]
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| 66 |
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set_property PACKAGE_PIN "D12" [get_ports "MIO[46]"]
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| 67 |
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set_property slew "slow" [get_ports "MIO[46]"]
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| 68 |
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set_property drive "8" [get_ports "MIO[46]"]
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| 69 |
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set_property pullup "TRUE" [get_ports "MIO[46]"]
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| 70 |
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# SD 0 / data[3] / MIO[45]
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| 71 |
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set_property iostandard "LVCMOS18" [get_ports "MIO[45]"]
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| 72 |
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set_property PACKAGE_PIN "B9" [get_ports "MIO[45]"]
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| 73 |
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set_property slew "fast" [get_ports "MIO[45]"]
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| 74 |
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set_property drive "8" [get_ports "MIO[45]"]
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| 75 |
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set_property pullup "TRUE" [get_ports "MIO[45]"]
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| 76 |
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# SD 0 / data[2] / MIO[44]
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| 77 |
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set_property iostandard "LVCMOS18" [get_ports "MIO[44]"]
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| 78 |
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set_property PACKAGE_PIN "E13" [get_ports "MIO[44]"]
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| 79 |
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set_property slew "fast" [get_ports "MIO[44]"]
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| 80 |
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set_property drive "8" [get_ports "MIO[44]"]
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| 81 |
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set_property pullup "TRUE" [get_ports "MIO[44]"]
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| 82 |
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# SD 0 / data[1] / MIO[43]
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| 83 |
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set_property iostandard "LVCMOS18" [get_ports "MIO[43]"]
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| 84 |
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set_property PACKAGE_PIN "B11" [get_ports "MIO[43]"]
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| 85 |
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set_property slew "fast" [get_ports "MIO[43]"]
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| 86 |
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set_property drive "8" [get_ports "MIO[43]"]
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| 87 |
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set_property pullup "TRUE" [get_ports "MIO[43]"]
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| 88 |
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# SD 0 / data[0] / MIO[42]
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| 89 |
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set_property iostandard "LVCMOS18" [get_ports "MIO[42]"]
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| 90 |
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set_property PACKAGE_PIN "D8" [get_ports "MIO[42]"]
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| 91 |
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set_property slew "fast" [get_ports "MIO[42]"]
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| 92 |
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set_property drive "8" [get_ports "MIO[42]"]
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| 93 |
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set_property pullup "TRUE" [get_ports "MIO[42]"]
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| 94 |
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# SD 0 / cmd / MIO[41]
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| 95 |
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set_property iostandard "LVCMOS18" [get_ports "MIO[41]"]
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| 96 |
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set_property PACKAGE_PIN "C8" [get_ports "MIO[41]"]
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| 97 |
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set_property slew "fast" [get_ports "MIO[41]"]
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| 98 |
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set_property drive "8" [get_ports "MIO[41]"]
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| 99 |
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set_property pullup "TRUE" [get_ports "MIO[41]"]
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| 100 |
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# SD 0 / clk / MIO[40]
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| 101 |
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set_property iostandard "LVCMOS18" [get_ports "MIO[40]"]
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| 102 |
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set_property PACKAGE_PIN "E14" [get_ports "MIO[40]"]
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| 103 |
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set_property slew "fast" [get_ports "MIO[40]"]
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| 104 |
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set_property drive "8" [get_ports "MIO[40]"]
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| 105 |
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set_property pullup "TRUE" [get_ports "MIO[40]"]
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| 106 |
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# USB 0 / data[7] / MIO[39]
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| 107 |
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set_property iostandard "LVCMOS18" [get_ports "MIO[39]"]
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| 108 |
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set_property PACKAGE_PIN "C13" [get_ports "MIO[39]"]
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| 109 |
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set_property slew "fast" [get_ports "MIO[39]"]
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| 110 |
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set_property drive "8" [get_ports "MIO[39]"]
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| 111 |
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set_property pullup "TRUE" [get_ports "MIO[39]"]
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| 112 |
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# USB 0 / data[6] / MIO[38]
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| 113 |
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set_property iostandard "LVCMOS18" [get_ports "MIO[38]"]
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| 114 |
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set_property PACKAGE_PIN "F13" [get_ports "MIO[38]"]
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| 115 |
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set_property slew "fast" [get_ports "MIO[38]"]
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| 116 |
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set_property drive "8" [get_ports "MIO[38]"]
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| 117 |
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set_property pullup "TRUE" [get_ports "MIO[38]"]
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| 118 |
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# USB 0 / data[5] / MIO[37]
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| 119 |
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set_property iostandard "LVCMOS18" [get_ports "MIO[37]"]
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| 120 |
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set_property PACKAGE_PIN "B14" [get_ports "MIO[37]"]
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| 121 |
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set_property slew "fast" [get_ports "MIO[37]"]
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| 122 |
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set_property drive "8" [get_ports "MIO[37]"]
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| 123 |
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set_property pullup "TRUE" [get_ports "MIO[37]"]
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| 124 |
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# USB 0 / clk / MIO[36]
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| 125 |
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set_property iostandard "LVCMOS18" [get_ports "MIO[36]"]
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| 126 |
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set_property PACKAGE_PIN "A9" [get_ports "MIO[36]"]
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| 127 |
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set_property slew "fast" [get_ports "MIO[36]"]
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| 128 |
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set_property drive "8" [get_ports "MIO[36]"]
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| 129 |
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set_property pullup "TRUE" [get_ports "MIO[36]"]
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| 130 |
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# USB 0 / data[3] / MIO[35]
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| 131 |
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set_property iostandard "LVCMOS18" [get_ports "MIO[35]"]
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| 132 |
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set_property PACKAGE_PIN "F14" [get_ports "MIO[35]"]
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| 133 |
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set_property slew "fast" [get_ports "MIO[35]"]
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| 134 |
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set_property drive "8" [get_ports "MIO[35]"]
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| 135 |
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set_property pullup "TRUE" [get_ports "MIO[35]"]
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| 136 |
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# USB 0 / data[2] / MIO[34]
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| 137 |
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set_property iostandard "LVCMOS18" [get_ports "MIO[34]"]
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| 138 |
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set_property PACKAGE_PIN "B12" [get_ports "MIO[34]"]
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| 139 |
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set_property slew "fast" [get_ports "MIO[34]"]
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| 140 |
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set_property drive "8" [get_ports "MIO[34]"]
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| 141 |
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set_property pullup "TRUE" [get_ports "MIO[34]"]
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| 142 |
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# USB 0 / data[1] / MIO[33]
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| 143 |
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set_property iostandard "LVCMOS18" [get_ports "MIO[33]"]
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| 144 |
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set_property PACKAGE_PIN "G13" [get_ports "MIO[33]"]
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| 145 |
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set_property slew "fast" [get_ports "MIO[33]"]
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| 146 |
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set_property drive "8" [get_ports "MIO[33]"]
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| 147 |
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set_property pullup "TRUE" [get_ports "MIO[33]"]
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| 148 |
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# USB 0 / data[0] / MIO[32]
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| 149 |
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set_property iostandard "LVCMOS18" [get_ports "MIO[32]"]
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| 150 |
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set_property PACKAGE_PIN "C7" [get_ports "MIO[32]"]
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| 151 |
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set_property slew "fast" [get_ports "MIO[32]"]
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| 152 |
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set_property drive "8" [get_ports "MIO[32]"]
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| 153 |
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set_property pullup "TRUE" [get_ports "MIO[32]"]
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| 154 |
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# USB 0 / nxt / MIO[31]
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| 155 |
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set_property iostandard "LVCMOS18" [get_ports "MIO[31]"]
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| 156 |
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set_property PACKAGE_PIN "F9" [get_ports "MIO[31]"]
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| 157 |
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set_property slew "fast" [get_ports "MIO[31]"]
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| 158 |
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set_property drive "8" [get_ports "MIO[31]"]
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| 159 |
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set_property pullup "TRUE" [get_ports "MIO[31]"]
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| 160 |
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# USB 0 / stp / MIO[30]
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| 161 |
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set_property iostandard "LVCMOS18" [get_ports "MIO[30]"]
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| 162 |
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set_property PACKAGE_PIN "A11" [get_ports "MIO[30]"]
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| 163 |
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set_property slew "fast" [get_ports "MIO[30]"]
|
| 164 |
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set_property drive "8" [get_ports "MIO[30]"]
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| 165 |
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set_property pullup "TRUE" [get_ports "MIO[30]"]
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| 166 |
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# USB 0 / dir / MIO[29]
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| 167 |
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set_property iostandard "LVCMOS18" [get_ports "MIO[29]"]
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| 168 |
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set_property PACKAGE_PIN "E8" [get_ports "MIO[29]"]
|
| 169 |
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set_property slew "fast" [get_ports "MIO[29]"]
|
| 170 |
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set_property drive "8" [get_ports "MIO[29]"]
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| 171 |
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set_property pullup "TRUE" [get_ports "MIO[29]"]
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| 172 |
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# USB 0 / data[4] / MIO[28]
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| 173 |
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set_property iostandard "LVCMOS18" [get_ports "MIO[28]"]
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| 174 |
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set_property PACKAGE_PIN "A12" [get_ports "MIO[28]"]
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| 175 |
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set_property slew "fast" [get_ports "MIO[28]"]
|
| 176 |
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set_property drive "8" [get_ports "MIO[28]"]
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| 177 |
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set_property pullup "TRUE" [get_ports "MIO[28]"]
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| 178 |
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# Enet 0 / rx_ctl / MIO[27]
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| 179 |
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set_property iostandard "HSTL_I_18" [get_ports "MIO[27]"]
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| 180 |
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set_property PACKAGE_PIN "D7" [get_ports "MIO[27]"]
|
| 181 |
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set_property slew "fast" [get_ports "MIO[27]"]
|
| 182 |
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set_property pullup "TRUE" [get_ports "MIO[27]"]
|
| 183 |
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# Enet 0 / rxd[3] / MIO[26]
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| 184 |
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set_property iostandard "HSTL_I_18" [get_ports "MIO[26]"]
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| 185 |
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set_property PACKAGE_PIN "A13" [get_ports "MIO[26]"]
|
| 186 |
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set_property slew "fast" [get_ports "MIO[26]"]
|
| 187 |
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set_property pullup "TRUE" [get_ports "MIO[26]"]
|
| 188 |
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# Enet 0 / rxd[2] / MIO[25]
|
| 189 |
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set_property iostandard "HSTL_I_18" [get_ports "MIO[25]"]
|
| 190 |
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set_property PACKAGE_PIN "F12" [get_ports "MIO[25]"]
|
| 191 |
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set_property slew "fast" [get_ports "MIO[25]"]
|
| 192 |
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set_property pullup "TRUE" [get_ports "MIO[25]"]
|
| 193 |
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# Enet 0 / rxd[1] / MIO[24]
|
| 194 |
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set_property iostandard "HSTL_I_18" [get_ports "MIO[24]"]
|
| 195 |
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set_property PACKAGE_PIN "B7" [get_ports "MIO[24]"]
|
| 196 |
|
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set_property slew "fast" [get_ports "MIO[24]"]
|
| 197 |
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set_property pullup "TRUE" [get_ports "MIO[24]"]
|
| 198 |
|
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# Enet 0 / rxd[0] / MIO[23]
|
| 199 |
|
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set_property iostandard "HSTL_I_18" [get_ports "MIO[23]"]
|
| 200 |
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set_property PACKAGE_PIN "E11" [get_ports "MIO[23]"]
|
| 201 |
|
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set_property slew "fast" [get_ports "MIO[23]"]
|
| 202 |
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set_property pullup "TRUE" [get_ports "MIO[23]"]
|
| 203 |
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# Enet 0 / rx_clk / MIO[22]
|
| 204 |
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set_property iostandard "HSTL_I_18" [get_ports "MIO[22]"]
|
| 205 |
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set_property PACKAGE_PIN "A14" [get_ports "MIO[22]"]
|
| 206 |
|
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set_property slew "fast" [get_ports "MIO[22]"]
|
| 207 |
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set_property pullup "TRUE" [get_ports "MIO[22]"]
|
| 208 |
|
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# Enet 0 / tx_ctl / MIO[21]
|
| 209 |
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set_property iostandard "HSTL_I_18" [get_ports "MIO[21]"]
|
| 210 |
|
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set_property PACKAGE_PIN "F11" [get_ports "MIO[21]"]
|
| 211 |
|
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set_property slew "fast" [get_ports "MIO[21]"]
|
| 212 |
|
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set_property pullup "TRUE" [get_ports "MIO[21]"]
|
| 213 |
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# Enet 0 / txd[3] / MIO[20]
|
| 214 |
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set_property iostandard "HSTL_I_18" [get_ports "MIO[20]"]
|
| 215 |
|
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set_property PACKAGE_PIN "A8" [get_ports "MIO[20]"]
|
| 216 |
|
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set_property slew "fast" [get_ports "MIO[20]"]
|
| 217 |
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set_property pullup "TRUE" [get_ports "MIO[20]"]
|
| 218 |
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# Enet 0 / txd[2] / MIO[19]
|
| 219 |
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set_property iostandard "HSTL_I_18" [get_ports "MIO[19]"]
|
| 220 |
|
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set_property PACKAGE_PIN "E10" [get_ports "MIO[19]"]
|
| 221 |
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set_property slew "fast" [get_ports "MIO[19]"]
|
| 222 |
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set_property pullup "TRUE" [get_ports "MIO[19]"]
|
| 223 |
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# Enet 0 / txd[1] / MIO[18]
|
| 224 |
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set_property iostandard "HSTL_I_18" [get_ports "MIO[18]"]
|
| 225 |
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set_property PACKAGE_PIN "A7" [get_ports "MIO[18]"]
|
| 226 |
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set_property slew "fast" [get_ports "MIO[18]"]
|
| 227 |
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set_property pullup "TRUE" [get_ports "MIO[18]"]
|
| 228 |
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# Enet 0 / txd[0] / MIO[17]
|
| 229 |
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set_property iostandard "HSTL_I_18" [get_ports "MIO[17]"]
|
| 230 |
|
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set_property PACKAGE_PIN "E9" [get_ports "MIO[17]"]
|
| 231 |
|
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set_property slew "fast" [get_ports "MIO[17]"]
|
| 232 |
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set_property pullup "TRUE" [get_ports "MIO[17]"]
|
| 233 |
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# Enet 0 / tx_clk / MIO[16]
|
| 234 |
|
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set_property iostandard "HSTL_I_18" [get_ports "MIO[16]"]
|
| 235 |
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set_property PACKAGE_PIN "D6" [get_ports "MIO[16]"]
|
| 236 |
|
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set_property slew "fast" [get_ports "MIO[16]"]
|
| 237 |
|
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set_property pullup "TRUE" [get_ports "MIO[16]"]
|
| 238 |
|
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# SD 0 / wp / MIO[15]
|
| 239 |
|
|
set_property iostandard "LVCMOS18" [get_ports "MIO[15]"]
|
| 240 |
|
|
set_property PACKAGE_PIN "E6" [get_ports "MIO[15]"]
|
| 241 |
|
|
set_property slew "fast" [get_ports "MIO[15]"]
|
| 242 |
|
|
set_property drive "8" [get_ports "MIO[15]"]
|
| 243 |
|
|
set_property pullup "TRUE" [get_ports "MIO[15]"]
|
| 244 |
|
|
# GPIO / gpio[14] / MIO[14]
|
| 245 |
|
|
set_property iostandard "LVCMOS18" [get_ports "MIO[14]"]
|
| 246 |
|
|
set_property PACKAGE_PIN "B6" [get_ports "MIO[14]"]
|
| 247 |
|
|
set_property slew "slow" [get_ports "MIO[14]"]
|
| 248 |
|
|
set_property drive "8" [get_ports "MIO[14]"]
|
| 249 |
|
|
set_property pullup "TRUE" [get_ports "MIO[14]"]
|
| 250 |
|
|
# GPIO / gpio[13] / MIO[13]
|
| 251 |
|
|
set_property iostandard "LVCMOS18" [get_ports "MIO[13]"]
|
| 252 |
|
|
set_property PACKAGE_PIN "A6" [get_ports "MIO[13]"]
|
| 253 |
|
|
set_property slew "slow" [get_ports "MIO[13]"]
|
| 254 |
|
|
set_property drive "8" [get_ports "MIO[13]"]
|
| 255 |
|
|
set_property pullup "TRUE" [get_ports "MIO[13]"]
|
| 256 |
|
|
# GPIO / gpio[12] / MIO[12]
|
| 257 |
|
|
set_property iostandard "LVCMOS18" [get_ports "MIO[12]"]
|
| 258 |
|
|
set_property PACKAGE_PIN "C5" [get_ports "MIO[12]"]
|
| 259 |
|
|
set_property slew "slow" [get_ports "MIO[12]"]
|
| 260 |
|
|
set_property drive "8" [get_ports "MIO[12]"]
|
| 261 |
|
|
set_property pullup "TRUE" [get_ports "MIO[12]"]
|
| 262 |
|
|
# GPIO / gpio[11] / MIO[11]
|
| 263 |
|
|
set_property iostandard "LVCMOS18" [get_ports "MIO[11]"]
|
| 264 |
|
|
set_property PACKAGE_PIN "B4" [get_ports "MIO[11]"]
|
| 265 |
|
|
set_property slew "slow" [get_ports "MIO[11]"]
|
| 266 |
|
|
set_property drive "8" [get_ports "MIO[11]"]
|
| 267 |
|
|
set_property pullup "TRUE" [get_ports "MIO[11]"]
|
| 268 |
|
|
# GPIO / gpio[10] / MIO[10]
|
| 269 |
|
|
set_property iostandard "LVCMOS18" [get_ports "MIO[10]"]
|
| 270 |
|
|
set_property PACKAGE_PIN "G7" [get_ports "MIO[10]"]
|
| 271 |
|
|
set_property slew "slow" [get_ports "MIO[10]"]
|
| 272 |
|
|
set_property drive "8" [get_ports "MIO[10]"]
|
| 273 |
|
|
set_property pullup "TRUE" [get_ports "MIO[10]"]
|
| 274 |
|
|
# GPIO / gpio[9] / MIO[9]
|
| 275 |
|
|
set_property iostandard "LVCMOS18" [get_ports "MIO[9]"]
|
| 276 |
|
|
set_property PACKAGE_PIN "C4" [get_ports "MIO[9]"]
|
| 277 |
|
|
set_property slew "slow" [get_ports "MIO[9]"]
|
| 278 |
|
|
set_property drive "8" [get_ports "MIO[9]"]
|
| 279 |
|
|
set_property pullup "TRUE" [get_ports "MIO[9]"]
|
| 280 |
|
|
# Quad SPI Flash / qspi_fbclk / MIO[8]
|
| 281 |
|
|
set_property iostandard "LVCMOS18" [get_ports "MIO[8]"]
|
| 282 |
|
|
set_property PACKAGE_PIN "E5" [get_ports "MIO[8]"]
|
| 283 |
|
|
set_property slew "slow" [get_ports "MIO[8]"]
|
| 284 |
|
|
set_property drive "8" [get_ports "MIO[8]"]
|
| 285 |
|
|
# GPIO / gpio[7] / MIO[7]
|
| 286 |
|
|
set_property iostandard "LVCMOS18" [get_ports "MIO[7]"]
|
| 287 |
|
|
set_property PACKAGE_PIN "D5" [get_ports "MIO[7]"]
|
| 288 |
|
|
set_property slew "slow" [get_ports "MIO[7]"]
|
| 289 |
|
|
set_property drive "8" [get_ports "MIO[7]"]
|
| 290 |
|
|
# Quad SPI Flash / qspi0_sclk / MIO[6]
|
| 291 |
|
|
set_property iostandard "LVCMOS18" [get_ports "MIO[6]"]
|
| 292 |
|
|
set_property PACKAGE_PIN "A4" [get_ports "MIO[6]"]
|
| 293 |
|
|
set_property slew "fast" [get_ports "MIO[6]"]
|
| 294 |
|
|
set_property drive "8" [get_ports "MIO[6]"]
|
| 295 |
|
|
# Quad SPI Flash / qspi0_io[3] / MIO[5]
|
| 296 |
|
|
set_property iostandard "LVCMOS18" [get_ports "MIO[5]"]
|
| 297 |
|
|
set_property PACKAGE_PIN "A3" [get_ports "MIO[5]"]
|
| 298 |
|
|
set_property slew "fast" [get_ports "MIO[5]"]
|
| 299 |
|
|
set_property drive "8" [get_ports "MIO[5]"]
|
| 300 |
|
|
# Quad SPI Flash / qspi0_io[2] / MIO[4]
|
| 301 |
|
|
set_property iostandard "LVCMOS18" [get_ports "MIO[4]"]
|
| 302 |
|
|
set_property PACKAGE_PIN "E4" [get_ports "MIO[4]"]
|
| 303 |
|
|
set_property slew "fast" [get_ports "MIO[4]"]
|
| 304 |
|
|
set_property drive "8" [get_ports "MIO[4]"]
|
| 305 |
|
|
# Quad SPI Flash / qspi0_io[1] / MIO[3]
|
| 306 |
|
|
set_property iostandard "LVCMOS18" [get_ports "MIO[3]"]
|
| 307 |
|
|
set_property PACKAGE_PIN "F6" [get_ports "MIO[3]"]
|
| 308 |
|
|
set_property slew "fast" [get_ports "MIO[3]"]
|
| 309 |
|
|
set_property drive "8" [get_ports "MIO[3]"]
|
| 310 |
|
|
# Quad SPI Flash / qspi0_io[0] / MIO[2]
|
| 311 |
|
|
set_property iostandard "LVCMOS18" [get_ports "MIO[2]"]
|
| 312 |
|
|
set_property PACKAGE_PIN "A2" [get_ports "MIO[2]"]
|
| 313 |
|
|
set_property slew "fast" [get_ports "MIO[2]"]
|
| 314 |
|
|
set_property drive "8" [get_ports "MIO[2]"]
|
| 315 |
|
|
# Quad SPI Flash / qspi0_ss_b / MIO[1]
|
| 316 |
|
|
set_property iostandard "LVCMOS18" [get_ports "MIO[1]"]
|
| 317 |
|
|
set_property PACKAGE_PIN "A1" [get_ports "MIO[1]"]
|
| 318 |
|
|
set_property slew "fast" [get_ports "MIO[1]"]
|
| 319 |
|
|
set_property drive "8" [get_ports "MIO[1]"]
|
| 320 |
|
|
set_property pullup "TRUE" [get_ports "MIO[1]"]
|
| 321 |
|
|
# SD 0 / cd / MIO[0]
|
| 322 |
|
|
set_property iostandard "LVCMOS18" [get_ports "MIO[0]"]
|
| 323 |
|
|
set_property PACKAGE_PIN "G6" [get_ports "MIO[0]"]
|
| 324 |
|
|
set_property slew "fast" [get_ports "MIO[0]"]
|
| 325 |
|
|
set_property drive "8" [get_ports "MIO[0]"]
|
| 326 |
|
|
set_property pullup "TRUE" [get_ports "MIO[0]"]
|
| 327 |
|
|
set_property iostandard "SSTL15" [get_ports "DDR_WEB"]
|
| 328 |
|
|
set_property PACKAGE_PIN "R4" [get_ports "DDR_WEB"]
|
| 329 |
|
|
set_property slew "FAST" [get_ports "DDR_WEB"]
|
| 330 |
|
|
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_VRP"]
|
| 331 |
|
|
set_property PACKAGE_PIN "N7" [get_ports "DDR_VRP"]
|
| 332 |
|
|
set_property slew "FAST" [get_ports "DDR_VRP"]
|
| 333 |
|
|
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_VRN"]
|
| 334 |
|
|
set_property PACKAGE_PIN "M7" [get_ports "DDR_VRN"]
|
| 335 |
|
|
set_property slew "FAST" [get_ports "DDR_VRN"]
|
| 336 |
|
|
set_property iostandard "SSTL15" [get_ports "DDR_RAS_n"]
|
| 337 |
|
|
set_property PACKAGE_PIN "R5" [get_ports "DDR_RAS_n"]
|
| 338 |
|
|
set_property slew "FAST" [get_ports "DDR_RAS_n"]
|
| 339 |
|
|
set_property iostandard "SSTL15" [get_ports "DDR_ODT"]
|
| 340 |
|
|
set_property PACKAGE_PIN "P5" [get_ports "DDR_ODT"]
|
| 341 |
|
|
set_property slew "FAST" [get_ports "DDR_ODT"]
|
| 342 |
|
|
set_property iostandard "SSTL15" [get_ports "DDR_DRSTB"]
|
| 343 |
|
|
set_property PACKAGE_PIN "F3" [get_ports "DDR_DRSTB"]
|
| 344 |
|
|
set_property slew "FAST" [get_ports "DDR_DRSTB"]
|
| 345 |
|
|
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[3]"]
|
| 346 |
|
|
set_property PACKAGE_PIN "V2" [get_ports "DDR_DQS[3]"]
|
| 347 |
|
|
set_property slew "FAST" [get_ports "DDR_DQS[3]"]
|
| 348 |
|
|
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[2]"]
|
| 349 |
|
|
set_property PACKAGE_PIN "N2" [get_ports "DDR_DQS[2]"]
|
| 350 |
|
|
set_property slew "FAST" [get_ports "DDR_DQS[2]"]
|
| 351 |
|
|
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[1]"]
|
| 352 |
|
|
set_property PACKAGE_PIN "H2" [get_ports "DDR_DQS[1]"]
|
| 353 |
|
|
set_property slew "FAST" [get_ports "DDR_DQS[1]"]
|
| 354 |
|
|
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS[0]"]
|
| 355 |
|
|
set_property PACKAGE_PIN "C2" [get_ports "DDR_DQS[0]"]
|
| 356 |
|
|
set_property slew "FAST" [get_ports "DDR_DQS[0]"]
|
| 357 |
|
|
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[3]"]
|
| 358 |
|
|
set_property PACKAGE_PIN "W2" [get_ports "DDR_DQS_n[3]"]
|
| 359 |
|
|
set_property slew "FAST" [get_ports "DDR_DQS_n[3]"]
|
| 360 |
|
|
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[2]"]
|
| 361 |
|
|
set_property PACKAGE_PIN "P2" [get_ports "DDR_DQS_n[2]"]
|
| 362 |
|
|
set_property slew "FAST" [get_ports "DDR_DQS_n[2]"]
|
| 363 |
|
|
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[1]"]
|
| 364 |
|
|
set_property PACKAGE_PIN "J2" [get_ports "DDR_DQS_n[1]"]
|
| 365 |
|
|
set_property slew "FAST" [get_ports "DDR_DQS_n[1]"]
|
| 366 |
|
|
set_property iostandard "DIFF_SSTL15_T_DCI" [get_ports "DDR_DQS_n[0]"]
|
| 367 |
|
|
set_property PACKAGE_PIN "D2" [get_ports "DDR_DQS_n[0]"]
|
| 368 |
|
|
set_property slew "FAST" [get_ports "DDR_DQS_n[0]"]
|
| 369 |
|
|
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[9]"]
|
| 370 |
|
|
set_property PACKAGE_PIN "G1" [get_ports "DDR_DQ[9]"]
|
| 371 |
|
|
set_property slew "FAST" [get_ports "DDR_DQ[9]"]
|
| 372 |
|
|
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[8]"]
|
| 373 |
|
|
set_property PACKAGE_PIN "G2" [get_ports "DDR_DQ[8]"]
|
| 374 |
|
|
set_property slew "FAST" [get_ports "DDR_DQ[8]"]
|
| 375 |
|
|
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[7]"]
|
| 376 |
|
|
set_property PACKAGE_PIN "F1" [get_ports "DDR_DQ[7]"]
|
| 377 |
|
|
set_property slew "FAST" [get_ports "DDR_DQ[7]"]
|
| 378 |
|
|
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[6]"]
|
| 379 |
|
|
set_property PACKAGE_PIN "F2" [get_ports "DDR_DQ[6]"]
|
| 380 |
|
|
set_property slew "FAST" [get_ports "DDR_DQ[6]"]
|
| 381 |
|
|
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[5]"]
|
| 382 |
|
|
set_property PACKAGE_PIN "E1" [get_ports "DDR_DQ[5]"]
|
| 383 |
|
|
set_property slew "FAST" [get_ports "DDR_DQ[5]"]
|
| 384 |
|
|
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[4]"]
|
| 385 |
|
|
set_property PACKAGE_PIN "E3" [get_ports "DDR_DQ[4]"]
|
| 386 |
|
|
set_property slew "FAST" [get_ports "DDR_DQ[4]"]
|
| 387 |
|
|
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[3]"]
|
| 388 |
|
|
set_property PACKAGE_PIN "D3" [get_ports "DDR_DQ[3]"]
|
| 389 |
|
|
set_property slew "FAST" [get_ports "DDR_DQ[3]"]
|
| 390 |
|
|
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[31]"]
|
| 391 |
|
|
set_property PACKAGE_PIN "Y1" [get_ports "DDR_DQ[31]"]
|
| 392 |
|
|
set_property slew "FAST" [get_ports "DDR_DQ[31]"]
|
| 393 |
|
|
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[30]"]
|
| 394 |
|
|
set_property PACKAGE_PIN "W3" [get_ports "DDR_DQ[30]"]
|
| 395 |
|
|
set_property slew "FAST" [get_ports "DDR_DQ[30]"]
|
| 396 |
|
|
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[2]"]
|
| 397 |
|
|
set_property PACKAGE_PIN "B2" [get_ports "DDR_DQ[2]"]
|
| 398 |
|
|
set_property slew "FAST" [get_ports "DDR_DQ[2]"]
|
| 399 |
|
|
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[29]"]
|
| 400 |
|
|
set_property PACKAGE_PIN "Y3" [get_ports "DDR_DQ[29]"]
|
| 401 |
|
|
set_property slew "FAST" [get_ports "DDR_DQ[29]"]
|
| 402 |
|
|
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[28]"]
|
| 403 |
|
|
set_property PACKAGE_PIN "W1" [get_ports "DDR_DQ[28]"]
|
| 404 |
|
|
set_property slew "FAST" [get_ports "DDR_DQ[28]"]
|
| 405 |
|
|
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[27]"]
|
| 406 |
|
|
set_property PACKAGE_PIN "U2" [get_ports "DDR_DQ[27]"]
|
| 407 |
|
|
set_property slew "FAST" [get_ports "DDR_DQ[27]"]
|
| 408 |
|
|
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[26]"]
|
| 409 |
|
|
set_property PACKAGE_PIN "AA1" [get_ports "DDR_DQ[26]"]
|
| 410 |
|
|
set_property slew "FAST" [get_ports "DDR_DQ[26]"]
|
| 411 |
|
|
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[25]"]
|
| 412 |
|
|
set_property PACKAGE_PIN "U1" [get_ports "DDR_DQ[25]"]
|
| 413 |
|
|
set_property slew "FAST" [get_ports "DDR_DQ[25]"]
|
| 414 |
|
|
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[24]"]
|
| 415 |
|
|
set_property PACKAGE_PIN "AA3" [get_ports "DDR_DQ[24]"]
|
| 416 |
|
|
set_property slew "FAST" [get_ports "DDR_DQ[24]"]
|
| 417 |
|
|
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[23]"]
|
| 418 |
|
|
set_property PACKAGE_PIN "R1" [get_ports "DDR_DQ[23]"]
|
| 419 |
|
|
set_property slew "FAST" [get_ports "DDR_DQ[23]"]
|
| 420 |
|
|
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[22]"]
|
| 421 |
|
|
set_property PACKAGE_PIN "M2" [get_ports "DDR_DQ[22]"]
|
| 422 |
|
|
set_property slew "FAST" [get_ports "DDR_DQ[22]"]
|
| 423 |
|
|
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[21]"]
|
| 424 |
|
|
set_property PACKAGE_PIN "T2" [get_ports "DDR_DQ[21]"]
|
| 425 |
|
|
set_property slew "FAST" [get_ports "DDR_DQ[21]"]
|
| 426 |
|
|
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[20]"]
|
| 427 |
|
|
set_property PACKAGE_PIN "R3" [get_ports "DDR_DQ[20]"]
|
| 428 |
|
|
set_property slew "FAST" [get_ports "DDR_DQ[20]"]
|
| 429 |
|
|
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[1]"]
|
| 430 |
|
|
set_property PACKAGE_PIN "C3" [get_ports "DDR_DQ[1]"]
|
| 431 |
|
|
set_property slew "FAST" [get_ports "DDR_DQ[1]"]
|
| 432 |
|
|
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[19]"]
|
| 433 |
|
|
set_property PACKAGE_PIN "T1" [get_ports "DDR_DQ[19]"]
|
| 434 |
|
|
set_property slew "FAST" [get_ports "DDR_DQ[19]"]
|
| 435 |
|
|
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[18]"]
|
| 436 |
|
|
set_property PACKAGE_PIN "N3" [get_ports "DDR_DQ[18]"]
|
| 437 |
|
|
set_property slew "FAST" [get_ports "DDR_DQ[18]"]
|
| 438 |
|
|
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[17]"]
|
| 439 |
|
|
set_property PACKAGE_PIN "T3" [get_ports "DDR_DQ[17]"]
|
| 440 |
|
|
set_property slew "FAST" [get_ports "DDR_DQ[17]"]
|
| 441 |
|
|
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[16]"]
|
| 442 |
|
|
set_property PACKAGE_PIN "M1" [get_ports "DDR_DQ[16]"]
|
| 443 |
|
|
set_property slew "FAST" [get_ports "DDR_DQ[16]"]
|
| 444 |
|
|
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[15]"]
|
| 445 |
|
|
set_property PACKAGE_PIN "K3" [get_ports "DDR_DQ[15]"]
|
| 446 |
|
|
set_property slew "FAST" [get_ports "DDR_DQ[15]"]
|
| 447 |
|
|
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[14]"]
|
| 448 |
|
|
set_property PACKAGE_PIN "J1" [get_ports "DDR_DQ[14]"]
|
| 449 |
|
|
set_property slew "FAST" [get_ports "DDR_DQ[14]"]
|
| 450 |
|
|
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[13]"]
|
| 451 |
|
|
set_property PACKAGE_PIN "K1" [get_ports "DDR_DQ[13]"]
|
| 452 |
|
|
set_property slew "FAST" [get_ports "DDR_DQ[13]"]
|
| 453 |
|
|
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[12]"]
|
| 454 |
|
|
set_property PACKAGE_PIN "L3" [get_ports "DDR_DQ[12]"]
|
| 455 |
|
|
set_property slew "FAST" [get_ports "DDR_DQ[12]"]
|
| 456 |
|
|
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[11]"]
|
| 457 |
|
|
set_property PACKAGE_PIN "L2" [get_ports "DDR_DQ[11]"]
|
| 458 |
|
|
set_property slew "FAST" [get_ports "DDR_DQ[11]"]
|
| 459 |
|
|
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[10]"]
|
| 460 |
|
|
set_property PACKAGE_PIN "L1" [get_ports "DDR_DQ[10]"]
|
| 461 |
|
|
set_property slew "FAST" [get_ports "DDR_DQ[10]"]
|
| 462 |
|
|
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DQ[0]"]
|
| 463 |
|
|
set_property PACKAGE_PIN "D1" [get_ports "DDR_DQ[0]"]
|
| 464 |
|
|
set_property slew "FAST" [get_ports "DDR_DQ[0]"]
|
| 465 |
|
|
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[3]"]
|
| 466 |
|
|
set_property PACKAGE_PIN "AA2" [get_ports "DDR_DM[3]"]
|
| 467 |
|
|
set_property slew "FAST" [get_ports "DDR_DM[3]"]
|
| 468 |
|
|
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[2]"]
|
| 469 |
|
|
set_property PACKAGE_PIN "P1" [get_ports "DDR_DM[2]"]
|
| 470 |
|
|
set_property slew "FAST" [get_ports "DDR_DM[2]"]
|
| 471 |
|
|
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[1]"]
|
| 472 |
|
|
set_property PACKAGE_PIN "H3" [get_ports "DDR_DM[1]"]
|
| 473 |
|
|
set_property slew "FAST" [get_ports "DDR_DM[1]"]
|
| 474 |
|
|
set_property iostandard "SSTL15_T_DCI" [get_ports "DDR_DM[0]"]
|
| 475 |
|
|
set_property PACKAGE_PIN "B1" [get_ports "DDR_DM[0]"]
|
| 476 |
|
|
set_property slew "FAST" [get_ports "DDR_DM[0]"]
|
| 477 |
|
|
set_property iostandard "SSTL15" [get_ports "DDR_CS_n"]
|
| 478 |
|
|
set_property PACKAGE_PIN "P6" [get_ports "DDR_CS_n"]
|
| 479 |
|
|
set_property slew "FAST" [get_ports "DDR_CS_n"]
|
| 480 |
|
|
set_property iostandard "SSTL15" [get_ports "DDR_CKE"]
|
| 481 |
|
|
set_property PACKAGE_PIN "V3" [get_ports "DDR_CKE"]
|
| 482 |
|
|
set_property slew "FAST" [get_ports "DDR_CKE"]
|
| 483 |
|
|
set_property iostandard "DIFF_SSTL15" [get_ports "DDR_Clk"]
|
| 484 |
|
|
set_property PACKAGE_PIN "N4" [get_ports "DDR_Clk"]
|
| 485 |
|
|
set_property slew "FAST" [get_ports "DDR_Clk"]
|
| 486 |
|
|
set_property iostandard "DIFF_SSTL15" [get_ports "DDR_Clk_n"]
|
| 487 |
|
|
set_property PACKAGE_PIN "N5" [get_ports "DDR_Clk_n"]
|
| 488 |
|
|
set_property slew "FAST" [get_ports "DDR_Clk_n"]
|
| 489 |
|
|
set_property iostandard "SSTL15" [get_ports "DDR_CAS_n"]
|
| 490 |
|
|
set_property PACKAGE_PIN "P3" [get_ports "DDR_CAS_n"]
|
| 491 |
|
|
set_property slew "FAST" [get_ports "DDR_CAS_n"]
|
| 492 |
|
|
set_property iostandard "SSTL15" [get_ports "DDR_BankAddr[2]"]
|
| 493 |
|
|
set_property PACKAGE_PIN "M6" [get_ports "DDR_BankAddr[2]"]
|
| 494 |
|
|
set_property slew "FAST" [get_ports "DDR_BankAddr[2]"]
|
| 495 |
|
|
set_property iostandard "SSTL15" [get_ports "DDR_BankAddr[1]"]
|
| 496 |
|
|
set_property PACKAGE_PIN "L6" [get_ports "DDR_BankAddr[1]"]
|
| 497 |
|
|
set_property slew "FAST" [get_ports "DDR_BankAddr[1]"]
|
| 498 |
|
|
set_property iostandard "SSTL15" [get_ports "DDR_BankAddr[0]"]
|
| 499 |
|
|
set_property PACKAGE_PIN "L7" [get_ports "DDR_BankAddr[0]"]
|
| 500 |
|
|
set_property slew "FAST" [get_ports "DDR_BankAddr[0]"]
|
| 501 |
|
|
set_property iostandard "SSTL15" [get_ports "DDR_Addr[9]"]
|
| 502 |
|
|
set_property PACKAGE_PIN "H5" [get_ports "DDR_Addr[9]"]
|
| 503 |
|
|
set_property slew "FAST" [get_ports "DDR_Addr[9]"]
|
| 504 |
|
|
set_property iostandard "SSTL15" [get_ports "DDR_Addr[8]"]
|
| 505 |
|
|
set_property PACKAGE_PIN "J5" [get_ports "DDR_Addr[8]"]
|
| 506 |
|
|
set_property slew "FAST" [get_ports "DDR_Addr[8]"]
|
| 507 |
|
|
set_property iostandard "SSTL15" [get_ports "DDR_Addr[7]"]
|
| 508 |
|
|
set_property PACKAGE_PIN "J6" [get_ports "DDR_Addr[7]"]
|
| 509 |
|
|
set_property slew "FAST" [get_ports "DDR_Addr[7]"]
|
| 510 |
|
|
set_property iostandard "SSTL15" [get_ports "DDR_Addr[6]"]
|
| 511 |
|
|
set_property PACKAGE_PIN "J7" [get_ports "DDR_Addr[6]"]
|
| 512 |
|
|
set_property slew "FAST" [get_ports "DDR_Addr[6]"]
|
| 513 |
|
|
set_property iostandard "SSTL15" [get_ports "DDR_Addr[5]"]
|
| 514 |
|
|
set_property PACKAGE_PIN "K5" [get_ports "DDR_Addr[5]"]
|
| 515 |
|
|
set_property slew "FAST" [get_ports "DDR_Addr[5]"]
|
| 516 |
|
|
set_property iostandard "SSTL15" [get_ports "DDR_Addr[4]"]
|
| 517 |
|
|
set_property PACKAGE_PIN "K6" [get_ports "DDR_Addr[4]"]
|
| 518 |
|
|
set_property slew "FAST" [get_ports "DDR_Addr[4]"]
|
| 519 |
|
|
set_property iostandard "SSTL15" [get_ports "DDR_Addr[3]"]
|
| 520 |
|
|
set_property PACKAGE_PIN "L4" [get_ports "DDR_Addr[3]"]
|
| 521 |
|
|
set_property slew "FAST" [get_ports "DDR_Addr[3]"]
|
| 522 |
|
|
set_property iostandard "SSTL15" [get_ports "DDR_Addr[2]"]
|
| 523 |
|
|
set_property PACKAGE_PIN "K4" [get_ports "DDR_Addr[2]"]
|
| 524 |
|
|
set_property slew "FAST" [get_ports "DDR_Addr[2]"]
|
| 525 |
|
|
set_property iostandard "SSTL15" [get_ports "DDR_Addr[1]"]
|
| 526 |
|
|
set_property PACKAGE_PIN "M5" [get_ports "DDR_Addr[1]"]
|
| 527 |
|
|
set_property slew "FAST" [get_ports "DDR_Addr[1]"]
|
| 528 |
|
|
set_property iostandard "SSTL15" [get_ports "DDR_Addr[14]"]
|
| 529 |
|
|
set_property PACKAGE_PIN "G4" [get_ports "DDR_Addr[14]"]
|
| 530 |
|
|
set_property slew "FAST" [get_ports "DDR_Addr[14]"]
|
| 531 |
|
|
set_property iostandard "SSTL15" [get_ports "DDR_Addr[13]"]
|
| 532 |
|
|
set_property PACKAGE_PIN "F4" [get_ports "DDR_Addr[13]"]
|
| 533 |
|
|
set_property slew "FAST" [get_ports "DDR_Addr[13]"]
|
| 534 |
|
|
set_property iostandard "SSTL15" [get_ports "DDR_Addr[12]"]
|
| 535 |
|
|
set_property PACKAGE_PIN "H4" [get_ports "DDR_Addr[12]"]
|
| 536 |
|
|
set_property slew "FAST" [get_ports "DDR_Addr[12]"]
|
| 537 |
|
|
set_property iostandard "SSTL15" [get_ports "DDR_Addr[11]"]
|
| 538 |
|
|
set_property PACKAGE_PIN "G5" [get_ports "DDR_Addr[11]"]
|
| 539 |
|
|
set_property slew "FAST" [get_ports "DDR_Addr[11]"]
|
| 540 |
|
|
set_property iostandard "SSTL15" [get_ports "DDR_Addr[10]"]
|
| 541 |
|
|
set_property PACKAGE_PIN "J3" [get_ports "DDR_Addr[10]"]
|
| 542 |
|
|
set_property slew "FAST" [get_ports "DDR_Addr[10]"]
|
| 543 |
|
|
set_property iostandard "SSTL15" [get_ports "DDR_Addr[0]"]
|
| 544 |
|
|
set_property PACKAGE_PIN "M4" [get_ports "DDR_Addr[0]"]
|
| 545 |
|
|
set_property slew "FAST" [get_ports "DDR_Addr[0]"]
|
| 546 |
|
|
set_property iostandard "LVCMOS18" [get_ports "PS_PORB"]
|
| 547 |
|
|
set_property PACKAGE_PIN "B5" [get_ports "PS_PORB"]
|
| 548 |
|
|
set_property slew "fast" [get_ports "PS_PORB"]
|
| 549 |
|
|
set_property drive "8" [get_ports "PS_PORB"]
|
| 550 |
|
|
set_property iostandard "LVCMOS18" [get_ports "PS_SRSTB"]
|
| 551 |
|
|
set_property PACKAGE_PIN "C9" [get_ports "PS_SRSTB"]
|
| 552 |
|
|
set_property slew "fast" [get_ports "PS_SRSTB"]
|
| 553 |
|
|
set_property drive "8" [get_ports "PS_SRSTB"]
|
| 554 |
|
|
set_property iostandard "LVCMOS18" [get_ports "PS_CLK"]
|
| 555 |
|
|
set_property PACKAGE_PIN "F7" [get_ports "PS_CLK"]
|
| 556 |
|
|
set_property slew "fast" [get_ports "PS_CLK"]
|
| 557 |
|
|
set_property drive "8" [get_ports "PS_CLK"]
|
