URL https://opencores.org/ocsvn/bustap-jtag/bustap-jtag/trunk

Subversion Repositories bustap-jtag

[/] [bustap-jtag/] [trunk/] [par/] [xilinx/] [xps/] [zynq_bram.xmp] - Blame information for rev 20

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#Please do not modify this file by hand
XmpVersion: 14.3
VerMgmt: 14.3
IntStyle: default
Flow: ise
ModuleSearchPath: ../../../rtl/xilinx/pcores/bustap_jtag_v1_00_a/../../../
MHS File: zynq_bram.mhs
Architecture: zynq
Device: xc7z020
Package: clg484
SpeedGrade: -1
UserCmd1:
UserCmd1Type: 0
UserCmd2:
UserCmd2Type: 0
GenSimTB: 0
SdkExportBmmBit: 0
SdkExportDir: SDK/SDK_Export
InsertNoPads: 0
WarnForEAArch: 1
HdlLang: VERILOG
SimModel: BEHAVIORAL
ExternalMemSim: 0
UcfFile: data/zynq_bram.ucf
EnableParTimingError: 1
ShowLicenseDialog: 1
BInfo:
LockAddr: PL_bram_ctrl,C_S_AXI_BASEADDR
Processor: PS
ElfImp:
ElfSim:

Line No.	Rev	Author	Line
1	20	ash_riple	`#Please do not modify this file by hand`
2			`XmpVersion: 14.3`
3			`VerMgmt: 14.3`
4			`IntStyle: default`
5			`Flow: ise`
6			`ModuleSearchPath: ../../../rtl/xilinx/pcores/bustap_jtag_v1_00_a/../../../`
7			`MHS File: zynq_bram.mhs`
8			`Architecture: zynq`
9			`Device: xc7z020`
10			`Package: clg484`
11			`SpeedGrade: -1`
12			`UserCmd1:`
13			`UserCmd1Type: 0`
14			`UserCmd2:`
15			`UserCmd2Type: 0`
16			`GenSimTB: 0`
17			`SdkExportBmmBit: 0`
18			`SdkExportDir: SDK/SDK_Export`
19			`InsertNoPads: 0`
20			`WarnForEAArch: 1`
21			`HdlLang: VERILOG`
22			`SimModel: BEHAVIORAL`
23			`ExternalMemSim: 0`
24			`UcfFile: data/zynq_bram.ucf`
25			`EnableParTimingError: 1`
26			`ShowLicenseDialog: 1`
27			`BInfo:`
28			`LockAddr: PL_bram_ctrl,C_S_AXI_BASEADDR`
29			`Processor: PS`
30			`ElfImp:`
31			`ElfSim:`

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Subversion Repositories bustap-jtag

[/] [bustap-jtag/] [trunk/] [par/] [xilinx/] [xps/] [zynq_bram.xmp] - Blame information for rev 20