1 |
5 |
ash_riple |
//**************************************************************
|
2 |
|
|
// Module : up_monitor.v
|
3 |
18 |
ash_riple |
// Platform : Windows xp sp2, Ubuntu 10.04
|
4 |
5 |
ash_riple |
// Simulator : Modelsim 6.5b
|
5 |
18 |
ash_riple |
// Synthesizer : QuartusII 10.1 sp1, PlanAhead 14.2
|
6 |
|
|
// Place and Route : QuartusII 10.1 sp1, PlanAhead 14.2
|
7 |
|
|
// Targets device : Cyclone III, Zynq-7000
|
8 |
5 |
ash_riple |
// Author : Bibo Yang (ash_riple@hotmail.com)
|
9 |
|
|
// Organization : www.opencores.org
|
10 |
18 |
ash_riple |
// Revision : 2.3
|
11 |
|
|
// Date : 2012/11/19
|
12 |
|
|
// Description : Top level: transaction record generation
|
13 |
|
|
// and glue logic to group together
|
14 |
5 |
ash_riple |
// the JTAG input and output modules.
|
15 |
|
|
//**************************************************************
|
16 |
2 |
ash_riple |
|
17 |
5 |
ash_riple |
`timescale 1ns/1ns
|
18 |
18 |
ash_riple |
`include "vendor.h"
|
19 |
2 |
ash_riple |
|
20 |
5 |
ash_riple |
module up_monitor (
|
21 |
18 |
ash_riple |
`ifdef XILINX `ifdef AXI_IP
|
22 |
|
|
icontrol0, icontrol1, icontrol2,
|
23 |
|
|
`endif `endif
|
24 |
|
|
clk,
|
25 |
|
|
wr_en,rd_en,
|
26 |
|
|
addr_in,
|
27 |
|
|
data_in
|
28 |
5 |
ash_riple |
);
|
29 |
2 |
ash_riple |
|
30 |
18 |
ash_riple |
input clk;
|
31 |
|
|
input wr_en,rd_en;
|
32 |
|
|
input [15:2] addr_in;
|
33 |
|
|
input [31:0] data_in;
|
34 |
6 |
ash_riple |
/////////////////////////////////////////////////
|
35 |
|
|
// Registers and wires announcment
|
36 |
|
|
/////////////////////////////////////////////////
|
37 |
2 |
ash_riple |
|
38 |
6 |
ash_riple |
// for CPU bus signal buffer
|
39 |
|
|
reg wr_en_d1,rd_en_d1;
|
40 |
|
|
reg [15:2] addr_in_d1;
|
41 |
|
|
reg [31:0] data_in_d1;
|
42 |
|
|
// for capture address mask
|
43 |
|
|
wire [35:0] addr_mask0,addr_mask1,addr_mask2 ,addr_mask3 ,addr_mask4 ,addr_mask5 ,addr_mask6 ,addr_mask7 , // inclusive
|
44 |
|
|
addr_mask8,addr_mask9,addr_mask10,addr_mask11,addr_mask12,addr_mask13,addr_mask14,addr_mask15; // exclusive
|
45 |
|
|
wire [15:0] addr_mask_en = {addr_mask15[32],addr_mask14[32],addr_mask13[32],addr_mask12[32],
|
46 |
|
|
addr_mask11[32],addr_mask10[32],addr_mask9 [32],addr_mask8 [32],
|
47 |
|
|
addr_mask7 [32],addr_mask6 [32],addr_mask5 [32],addr_mask4 [32],
|
48 |
|
|
addr_mask3 [32],addr_mask2 [32],addr_mask1 [32],addr_mask0 [32]};
|
49 |
|
|
wire addr_wren = addr_mask15[35];
|
50 |
|
|
wire addr_rden = addr_mask15[34];
|
51 |
5 |
ash_riple |
reg addr_mask_ok;
|
52 |
6 |
ash_riple |
// for capture address+data trigger
|
53 |
|
|
wire [55:0] trig_cond;
|
54 |
|
|
wire trig_aden = trig_cond[55];
|
55 |
|
|
wire trig_daen = trig_cond[54];
|
56 |
|
|
wire trig_wren = trig_cond[51];
|
57 |
|
|
wire trig_rden = trig_cond[50];
|
58 |
5 |
ash_riple |
wire trig_en = trig_cond[49];
|
59 |
|
|
wire trig_set = trig_cond[48];
|
60 |
|
|
wire [15:0] trig_addr = trig_cond[47:32];
|
61 |
|
|
wire [31:0] trig_data = trig_cond[31:0];
|
62 |
6 |
ash_riple |
reg trig_cond_ok,trig_cond_ok_d1;
|
63 |
|
|
// for capture storage
|
64 |
12 |
ash_riple |
wire [81:0] capture_in;
|
65 |
5 |
ash_riple |
wire capture_wr;
|
66 |
11 |
ash_riple |
// for pretrigger capture
|
67 |
|
|
wire [9:0] pretrig_num;
|
68 |
|
|
reg [9:0] pretrig_cnt;
|
69 |
|
|
wire pretrig_full;
|
70 |
|
|
wire pretrig_wr;
|
71 |
|
|
reg pretrig_wr_d1,pretrig_rd;
|
72 |
12 |
ash_riple |
// for inter capture timer
|
73 |
|
|
reg [31:0] inter_cap_cnt;
|
74 |
5 |
ash_riple |
|
75 |
6 |
ash_riple |
/////////////////////////////////////////////////
|
76 |
|
|
// Capture logic main
|
77 |
|
|
/////////////////////////////////////////////////
|
78 |
|
|
|
79 |
5 |
ash_riple |
// bus input pipeline, allowing back-to-back/continuous bus access
|
80 |
|
|
always @(posedge clk)
|
81 |
2 |
ash_riple |
begin
|
82 |
5 |
ash_riple |
wr_en_d1 <= wr_en;
|
83 |
|
|
rd_en_d1 <= rd_en;
|
84 |
|
|
addr_in_d1 <= addr_in;
|
85 |
|
|
data_in_d1 <= data_in;
|
86 |
2 |
ash_riple |
end
|
87 |
|
|
|
88 |
5 |
ash_riple |
// address range based capture enable
|
89 |
|
|
always @(posedge clk)
|
90 |
2 |
ash_riple |
begin
|
91 |
6 |
ash_riple |
if (((addr_in[15:2]<=addr_mask0[31:18] && addr_in[15:2]>=addr_mask0[15:2] && addr_mask_en[ 0]) ||
|
92 |
|
|
(addr_in[15:2]<=addr_mask1[31:18] && addr_in[15:2]>=addr_mask1[15:2] && addr_mask_en[ 1]) ||
|
93 |
|
|
(addr_in[15:2]<=addr_mask2[31:18] && addr_in[15:2]>=addr_mask2[15:2] && addr_mask_en[ 2]) ||
|
94 |
|
|
(addr_in[15:2]<=addr_mask3[31:18] && addr_in[15:2]>=addr_mask3[15:2] && addr_mask_en[ 3]) ||
|
95 |
|
|
(addr_in[15:2]<=addr_mask4[31:18] && addr_in[15:2]>=addr_mask4[15:2] && addr_mask_en[ 4]) ||
|
96 |
|
|
(addr_in[15:2]<=addr_mask5[31:18] && addr_in[15:2]>=addr_mask5[15:2] && addr_mask_en[ 5]) ||
|
97 |
|
|
(addr_in[15:2]<=addr_mask6[31:18] && addr_in[15:2]>=addr_mask6[15:2] && addr_mask_en[ 6]) ||
|
98 |
|
|
(addr_in[15:2]<=addr_mask7[31:18] && addr_in[15:2]>=addr_mask7[15:2] && addr_mask_en[ 7])
|
99 |
|
|
) //inclusive address range set with individual enable: addr_mask 0 - 7
|
100 |
5 |
ash_riple |
&&
|
101 |
6 |
ash_riple |
((addr_in[15:2]>addr_mask8 [31:18] || addr_in[15:2]<addr_mask8 [15:2] || !addr_mask_en[ 8]) &&
|
102 |
|
|
(addr_in[15:2]>addr_mask9 [31:18] || addr_in[15:2]<addr_mask9 [15:2] || !addr_mask_en[ 9]) &&
|
103 |
|
|
(addr_in[15:2]>addr_mask10[31:18] || addr_in[15:2]<addr_mask10[15:2] || !addr_mask_en[10]) &&
|
104 |
|
|
(addr_in[15:2]>addr_mask11[31:18] || addr_in[15:2]<addr_mask11[15:2] || !addr_mask_en[11]) &&
|
105 |
|
|
(addr_in[15:2]>addr_mask12[31:18] || addr_in[15:2]<addr_mask12[15:2] || !addr_mask_en[12]) &&
|
106 |
|
|
(addr_in[15:2]>addr_mask13[31:18] || addr_in[15:2]<addr_mask13[15:2] || !addr_mask_en[13]) &&
|
107 |
|
|
(addr_in[15:2]>addr_mask14[31:18] || addr_in[15:2]<addr_mask14[15:2] || !addr_mask_en[14]) &&
|
108 |
|
|
(addr_in[15:2]>addr_mask15[31:18] || addr_in[15:2]<addr_mask15[15:2] || !addr_mask_en[15])
|
109 |
|
|
) //exclusive address range set with individual enable: addr_mask 8 - 15
|
110 |
2 |
ash_riple |
)
|
111 |
6 |
ash_riple |
addr_mask_ok <= (addr_rden && rd_en) || (addr_wren && wr_en);
|
112 |
5 |
ash_riple |
else
|
113 |
|
|
addr_mask_ok <= 0;
|
114 |
2 |
ash_riple |
end
|
115 |
|
|
|
116 |
6 |
ash_riple |
// address+data based capture trigger
|
117 |
5 |
ash_riple |
always @(posedge clk)
|
118 |
2 |
ash_riple |
begin
|
119 |
6 |
ash_riple |
if (trig_en==0) begin // trigger not enabled, trigger gate forced open
|
120 |
|
|
trig_cond_ok <= 1;
|
121 |
|
|
trig_cond_ok_d1 <= 1;
|
122 |
|
|
end
|
123 |
|
|
else if (trig_set==0) begin // trigger enabled and trigger stopped, trigger gate forced close
|
124 |
|
|
trig_cond_ok <= 0;
|
125 |
|
|
trig_cond_ok_d1 <= 0;
|
126 |
|
|
end
|
127 |
|
|
else begin // trigger enabled and trigger started, trigger gate conditional open
|
128 |
|
|
if ((trig_aden? trig_addr[15:2]==addr_in[15:2]: 1) && (trig_daen? trig_data==data_in: 1) &&
|
129 |
|
|
(trig_wren? wr_en : 1) && (trig_rden? rd_en : 1) &&
|
130 |
|
|
(rd_en || wr_en))
|
131 |
|
|
trig_cond_ok <= 1;
|
132 |
|
|
trig_cond_ok_d1 <= trig_cond_ok;
|
133 |
|
|
end
|
134 |
|
|
// trigger gate kept open until trigger stoped
|
135 |
2 |
ash_riple |
end
|
136 |
6 |
ash_riple |
wire trig_cond_ok_pulse = trig_cond_ok & !trig_cond_ok_d1;
|
137 |
2 |
ash_riple |
|
138 |
11 |
ash_riple |
// generate capture wr_in
|
139 |
12 |
ash_riple |
assign capture_in = {trig_cond_ok_pulse,wr_en_d1,inter_cap_cnt,addr_in_d1[15:2],2'b00,data_in_d1[31:0]};
|
140 |
13 |
ash_riple |
assign capture_wr = trig_cond_ok_pulse || (addr_mask_ok && trig_cond_ok);
|
141 |
2 |
ash_riple |
|
142 |
11 |
ash_riple |
// generate pre-trigger wr_in
|
143 |
|
|
assign pretrig_full = (pretrig_cnt >= pretrig_num) || trig_cond_ok;
|
144 |
|
|
assign pretrig_wr = (!trig_en || (trig_en && !trig_set))? 1'b0 : (trig_cond_ok? 1'b0 : addr_mask_ok);
|
145 |
|
|
always @(posedge clk)
|
146 |
|
|
begin
|
147 |
|
|
if (!trig_en || (trig_en && !trig_set)) begin
|
148 |
|
|
pretrig_cnt <= 10'd0;
|
149 |
|
|
pretrig_wr_d1<= 1'b0;
|
150 |
|
|
pretrig_rd <= 1'b0;
|
151 |
|
|
end
|
152 |
|
|
else if (!pretrig_full) begin
|
153 |
|
|
pretrig_cnt <= pretrig_cnt + addr_mask_ok;
|
154 |
|
|
pretrig_wr_d1<= 1'b0;
|
155 |
|
|
pretrig_rd <= 1'b0;
|
156 |
|
|
end
|
157 |
|
|
else if (pretrig_full) begin
|
158 |
|
|
pretrig_cnt <= pretrig_cnt;
|
159 |
|
|
pretrig_wr_d1<= pretrig_wr;
|
160 |
|
|
pretrig_rd <= pretrig_wr_d1;
|
161 |
|
|
end
|
162 |
|
|
end
|
163 |
|
|
|
164 |
12 |
ash_riple |
// generate interval counter
|
165 |
|
|
always @(posedge clk)
|
166 |
|
|
begin
|
167 |
|
|
if (capture_wr || pretrig_wr)
|
168 |
|
|
inter_cap_cnt <= 32'd0;
|
169 |
|
|
else if (inter_cap_cnt[31])
|
170 |
|
|
inter_cap_cnt <= 32'd3000000000;
|
171 |
|
|
else
|
172 |
|
|
inter_cap_cnt <= inter_cap_cnt + 32'd1;
|
173 |
|
|
end
|
174 |
|
|
|
175 |
6 |
ash_riple |
/////////////////////////////////////////////////
|
176 |
|
|
// Instantiate vendor specific JTAG functions
|
177 |
|
|
/////////////////////////////////////////////////
|
178 |
18 |
ash_riple |
`ifdef ALTERA
|
179 |
6 |
ash_riple |
// index 0, instantiate capture fifo, as output
|
180 |
|
|
virtual_jtag_adda_fifo u_virtual_jtag_adda_fifo (
|
181 |
|
|
.clk(clk),
|
182 |
11 |
ash_riple |
.wr_in(capture_wr || pretrig_wr),
|
183 |
|
|
.data_in(capture_in),
|
184 |
|
|
.rd_in(pretrig_rd)
|
185 |
6 |
ash_riple |
);
|
186 |
|
|
defparam
|
187 |
12 |
ash_riple |
u_virtual_jtag_adda_fifo.data_width = 82,
|
188 |
6 |
ash_riple |
u_virtual_jtag_adda_fifo.fifo_depth = 512,
|
189 |
|
|
u_virtual_jtag_adda_fifo.addr_width = 9,
|
190 |
|
|
u_virtual_jtag_adda_fifo.al_full_val = 511,
|
191 |
|
|
u_virtual_jtag_adda_fifo.al_empt_val = 0;
|
192 |
|
|
|
193 |
|
|
// index 1, instantiate capture mask, as input
|
194 |
2 |
ash_riple |
virtual_jtag_addr_mask u_virtual_jtag_addr_mask (
|
195 |
6 |
ash_riple |
// inclusive
|
196 |
2 |
ash_riple |
.mask_out0(addr_mask0),
|
197 |
|
|
.mask_out1(addr_mask1),
|
198 |
|
|
.mask_out2(addr_mask2),
|
199 |
|
|
.mask_out3(addr_mask3),
|
200 |
|
|
.mask_out4(addr_mask4),
|
201 |
|
|
.mask_out5(addr_mask5),
|
202 |
|
|
.mask_out6(addr_mask6),
|
203 |
|
|
.mask_out7(addr_mask7),
|
204 |
6 |
ash_riple |
// exclusive
|
205 |
2 |
ash_riple |
.mask_out8(addr_mask8),
|
206 |
|
|
.mask_out9(addr_mask9),
|
207 |
|
|
.mask_out10(addr_mask10),
|
208 |
|
|
.mask_out11(addr_mask11),
|
209 |
|
|
.mask_out12(addr_mask12),
|
210 |
|
|
.mask_out13(addr_mask13),
|
211 |
|
|
.mask_out14(addr_mask14),
|
212 |
|
|
.mask_out15(addr_mask15)
|
213 |
|
|
);
|
214 |
|
|
defparam
|
215 |
|
|
u_virtual_jtag_addr_mask.mask_index = 4,
|
216 |
6 |
ash_riple |
u_virtual_jtag_addr_mask.mask_enabl = 4,
|
217 |
|
|
u_virtual_jtag_addr_mask.addr_width = 32;
|
218 |
2 |
ash_riple |
|
219 |
6 |
ash_riple |
// index 2, instantiate capture trigger, as input
|
220 |
2 |
ash_riple |
virtual_jtag_adda_trig u_virtual_jtag_adda_trig (
|
221 |
11 |
ash_riple |
.trig_out(trig_cond),
|
222 |
|
|
.pnum_out(pretrig_num)
|
223 |
2 |
ash_riple |
);
|
224 |
|
|
defparam
|
225 |
11 |
ash_riple |
u_virtual_jtag_adda_trig.trig_width = 56,
|
226 |
|
|
u_virtual_jtag_adda_trig.pnum_width = 10;
|
227 |
18 |
ash_riple |
`endif
|
228 |
2 |
ash_riple |
|
229 |
18 |
ash_riple |
`ifdef XILINX
|
230 |
|
|
|
231 |
|
|
`ifdef AXI_IP
|
232 |
|
|
// external ICON
|
233 |
|
|
inout [35:0] icontrol0, icontrol1, icontrol2;
|
234 |
|
|
`else
|
235 |
|
|
// internal ICON
|
236 |
|
|
wire [35:0] icontrol0, icontrol1, icontrol2;
|
237 |
|
|
`endif
|
238 |
|
|
|
239 |
|
|
// index 0, instantiate capture fifo, as output
|
240 |
|
|
chipscope_vio_adda_fifo u_chipscope_vio_adda_fifo (
|
241 |
|
|
.wr_in(capture_wr || pretrig_wr),
|
242 |
|
|
.data_in(capture_in),
|
243 |
|
|
.rd_in(pretrig_rd),
|
244 |
|
|
.clk(clk),
|
245 |
|
|
.icon_ctrl(icontrol0)
|
246 |
|
|
);
|
247 |
|
|
defparam
|
248 |
|
|
u_chipscope_vio_adda_fifo.data_width = 82,
|
249 |
|
|
u_chipscope_vio_adda_fifo.addr_width = 10,
|
250 |
|
|
u_chipscope_vio_adda_fifo.al_full_val = 511;
|
251 |
|
|
|
252 |
|
|
// index 1, instantiate capture mask, as input
|
253 |
|
|
chipscope_vio_addr_mask u_chipscope_vio_addr_mask (
|
254 |
|
|
// inclusive
|
255 |
|
|
.mask_out0(addr_mask0),
|
256 |
|
|
.mask_out1(addr_mask1),
|
257 |
|
|
.mask_out2(addr_mask2),
|
258 |
|
|
.mask_out3(addr_mask3),
|
259 |
|
|
.mask_out4(addr_mask4),
|
260 |
|
|
.mask_out5(addr_mask5),
|
261 |
|
|
.mask_out6(addr_mask6),
|
262 |
|
|
.mask_out7(addr_mask7),
|
263 |
|
|
// exclusive
|
264 |
|
|
.mask_out8(addr_mask8),
|
265 |
|
|
.mask_out9(addr_mask9),
|
266 |
|
|
.mask_out10(addr_mask10),
|
267 |
|
|
.mask_out11(addr_mask11),
|
268 |
|
|
.mask_out12(addr_mask12),
|
269 |
|
|
.mask_out13(addr_mask13),
|
270 |
|
|
.mask_out14(addr_mask14),
|
271 |
|
|
.mask_out15(addr_mask15),
|
272 |
|
|
.clk(clk),
|
273 |
|
|
.icon_ctrl(icontrol1)
|
274 |
|
|
);
|
275 |
|
|
defparam
|
276 |
|
|
u_chipscope_vio_addr_mask.mask_index = 4,
|
277 |
|
|
u_chipscope_vio_addr_mask.mask_enabl = 4,
|
278 |
|
|
u_chipscope_vio_addr_mask.addr_width = 32;
|
279 |
|
|
|
280 |
|
|
// index 2, instantiate capture trigger, as input
|
281 |
|
|
chipscope_vio_adda_trig u_chipscope_vio_adda_trig (
|
282 |
|
|
.trig_out(trig_cond),
|
283 |
|
|
.pnum_out(pretrig_num),
|
284 |
|
|
.clk(clk),
|
285 |
|
|
.icon_ctrl(icontrol2)
|
286 |
|
|
);
|
287 |
|
|
defparam
|
288 |
|
|
u_chipscope_vio_adda_trig.trig_width = 56,
|
289 |
|
|
u_chipscope_vio_adda_trig.pnum_width = 10;
|
290 |
|
|
|
291 |
|
|
`ifdef AXI_IP
|
292 |
|
|
// external ICON
|
293 |
|
|
`else
|
294 |
|
|
// internal ICON
|
295 |
|
|
chipscope_icon u_chipscope_icon (
|
296 |
|
|
.CONTROL0(icontrol0),
|
297 |
|
|
.CONTROL1(icontrol1),
|
298 |
|
|
.CONTROL2(icontrol2)
|
299 |
|
|
);
|
300 |
|
|
`endif
|
301 |
|
|
|
302 |
|
|
`endif
|
303 |
|
|
|
304 |
2 |
ash_riple |
endmodule
|