Subversion Repositories bustap-jtag

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# Xilinx Core Generator version 14.2

# Date: Mon Nov 19 14:30:49 2012

#

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#

#  This file contains the customisation parameters for a

#  Xilinx CORE Generator IP GUI. It is strongly recommended

#  that you do not manually alter this file as it may cause

#  unexpected and unsupported behavior.

#

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#

#  Generated from component: xilinx.com:ip:chipscope_icon:1.06.a

#

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#

# BEGIN Project Options

SET addpads = false

SET asysymbol = true

SET busformat = BusFormatAngleBracketNotRipped

SET createndf = false

SET designentry = Verilog

SET device = xc7z020

SET devicefamily = zynq

SET flowvendor = Other

SET formalverification = false

SET foundationsym = false

SET implementationfiletype = Ngc

SET package = clg400

SET removerpms = false

SET simulationfiles = Behavioral

SET speedgrade = -2

SET verilogsim = true

SET vhdlsim = false

# END Project Options

# BEGIN Select

SELECT ICON_(ChipScope_Pro_-_Integrated_Controller) family Xilinx,_Inc. 1.06.a

# END Select

# BEGIN Parameters

CSET component_name=chipscope_icon

CSET constraint_type=external

CSET enable_jtag_bufg=true

CSET example_design=false

CSET number_control_ports=3

CSET use_ext_bscan=false

CSET use_softbscan=false

CSET use_unused_bscan=false

CSET user_scan_chain=USER1

# END Parameters

# BEGIN Extra information

MISC pkg_timestamp=2012-07-21T03:11:48Z

# END Extra information

GENERATE

# CRC: 868ef601