URL https://opencores.org/ocsvn/bustap-jtag/bustap-jtag/trunk

Subversion Repositories bustap-jtag

[/] [bustap-jtag/] [trunk/] [rtl/] [xilinx/] [coregen/] [chipscope_vio_fifo.v] - Blame information for rev 20

Line No.	Rev	Author	Line
1	18	ash_riple	`///////////////////////////////////////////////////////////////////////////////`
2	20	ash_riple	`// Copyright (c) 2014 Xilinx, Inc.`
3	18	ash_riple	`// All Rights Reserved`
4			`///////////////////////////////////////////////////////////////////////////////`
5			`// ____ ____`
6			`// / /\/ /`
7			`// /___/ \ / Vendor : Xilinx`
8	20	ash_riple	`// \ \ \/ Version : 14.3`
9	18	ash_riple	`// \ \ Application: Xilinx CORE Generator`
10			`// / / Filename : chipscope_vio_fifo.v`
11	20	ash_riple	`// /___/ /\ Timestamp : Fri Feb 07 17:33:59 �й��׼ʱ�� 2014`
12	18	ash_riple	`// \ \ / \`
13			`// \___\/\___\`
14			`//`
15			`// Design Name: Verilog Synthesis Wrapper`
16			`///////////////////////////////////////////////////////////////////////////////`
17			`// This wrapper is used to integrate with Project Navigator and PlanAhead`
18
19			`timescale 1ns/1ps
20
21			`module chipscope_vio_fifo(`
22			`CONTROL,`
23			`CLK,`
24			`SYNC_IN,`
25	20	ash_riple	`SYNC_OUT) /* synthesis syn_black_box syn_noprune=1 */;`
26	18	ash_riple
27
28			`inout [35 : 0] CONTROL;`
29			`input CLK;`
30	20	ash_riple	`input [107 : 0] SYNC_IN;`
31	18	ash_riple	`output [1 : 0] SYNC_OUT;`
32
33			`endmodule`