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[/] [bustap-jtag/] [trunk/] [rtl/] [xilinx/] [coregen/] [coregen.cgc] - Blame information for rev 20

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   xilinx.com
   project
   coregen
   1.0
   
      
         chipscope_icon
         
         
            chipscope_icon
            false
            3
            true
            external
            false
            false
            USER1
            false
         
         
            
               
                  coregen
                  ./
                  ./tmp/
                  ./tmp/_cg/
               
               
                  xc7z020
                  zynq
                  clg400
                  -2
               
               
                  BusFormatAngleBracketNotRipped
                  Verilog
                  true
                  Other
                  false
                  false
                  false
                  Ngc
                  false
               
               
                  Behavioral
                  Verilog
                  false
               
               
                  2012-07-21+03:11
               
            
         
      
      
         chipscope_vio_fifo
         
         
            chipscope_vio_fifo
            108
            2
            false
            false
            external
            false
            8
            true
            8
            true
            true
            8
            1
            8
            1
            2
            2
            0
            108
            chipscope_vio_fifo
            true
            Component_Name=chipscope_vio_fifo;Enable_Synchronous_Input_Port=true;Enable_Synchronous_Output_Port=true;Enable_Asynchronous_Input_Port=false;Enable_Asynchronous_Output_Port=false;Synchronous_Input_Port_Width=108;Synchronous_Output_Port_Width=2;Asynchronous_Input_Port_Width=8;Asynchronous_Output_Port_Width=8;Invert_Clock_Input=false
            external
            0
            0
            1
         
         
            
               
                  coregen
                  ./
                  ./tmp/
                  ./tmp/_cg/
               
               
                  xc7z020
                  zynq
                  clg400
                  -2
               
               
                  BusFormatAngleBracketNotRipped
                  Verilog
                  true
                  Other
                  false
                  false
                  false
                  Ngc
                  false
               
               
                  Structural
                  Verilog
                  false
               
               
                  2012-10-12+23:08
               
            
            
               
                  customization_generator
               
               
                  model_parameter_resolution_generator
               
               
                  ip_xco_generator
                  
                     ./chipscope_vio_fifo.xco
                     xco
                     Fri Feb 07 09:32:54 GMT 2014
                     0x724012F7
                     generationID_1879581046
                  
               
               
                  ngc_netlist_generator
                  
                     ./chipscope_vio_fifo/example_design/chipscope_vio_fifo_bb_lib.v
                     ignore
                     verilogSynthesis
                     Fri Feb 07 09:32:54 GMT 2014
                     0xEC2F0FB0
                     generationID_1879581046
                  
                  
                     ./chipscope_vio_fifo/example_design/example_chipscope_vio_fifo.ucf
                     ignore
                     ucf
                     Fri Feb 07 09:32:57 GMT 2014
                     0x1390C322
                     generationID_1879581046
                  
                  
                     ./chipscope_vio_fifo/example_design/example_chipscope_vio_fifo.v
                     ignore
                     verilogSynthesis
                     Fri Feb 07 09:32:56 GMT 2014
                     0x8DB35830
                     generationID_1879581046
                  
                  
                     ./chipscope_vio_fifo/example_design/example_chipscope_vio_fifo.xdc
                     ignore
                     xdc
                     Fri Feb 07 09:32:57 GMT 2014
                     0x938BE115
                     generationID_1879581046
                  
                  
                     ./chipscope_vio_fifo/implement/chipscope_icon.xco
                     ignore
                     xco
                     Fri Feb 07 09:32:55 GMT 2014
                     0x1FF80BFB
                     generationID_1879581046
                  
                  
                     ./chipscope_vio_fifo/implement/coregen.cgp
                     ignore
                     unknown
                     Fri Feb 07 09:32:55 GMT 2014
                     0x940C30DF
                     generationID_1879581046
                  
                  
                     ./chipscope_vio_fifo/implement/example_chipscope_vio_fifo.prj
                     ignore
                     unknown
                     Fri Feb 07 09:32:56 GMT 2014
                     0xAE724F77
                     generationID_1879581046
                  
                  
                     ./chipscope_vio_fifo/implement/example_chipscope_vio_fifo.xst
                     ignore
                     unknown
                     Fri Feb 07 09:32:58 GMT 2014
                     0xEBBE356D
                     generationID_1879581046
                  
                  
                     ./chipscope_vio_fifo/implement/ise_implement.bat
                     ignore
                     unknown
                     Fri Feb 07 09:32:55 GMT 2014
                     0xEE86AB45
                     generationID_1879581046
                  
                  
                     ./chipscope_vio_fifo/implement/ise_implement.sh
                     ignore
                     unknown
                     Fri Feb 07 09:32:58 GMT 2014
                     0x32780610
                     generationID_1879581046
                  
                  
                     ./chipscope_vio_fifo/implement/pa_ise_implement.tcl
                     ignore
                     tcl
                     Fri Feb 07 09:32:56 GMT 2014
                     0xC8D9F8F9
                     generationID_1879581046
                  
                  
                     ./chipscope_vio_fifo/implement/rdi_implement.tcl
                     ignore
                     tcl
                     Fri Feb 07 09:32:57 GMT 2014
                     0xBD351EB6
                     generationID_1879581046
                  
                  
                     ./chipscope_vio_fifo/implement/v_rdi_implement.tcl
                     ignore
                     tcl
                     Fri Feb 07 09:32:58 GMT 2014
                     0x74FFDD3B
                     generationID_1879581046
                  
                  
                     ./chipscope_vio_fifo/read_me.txt
                     ignore
                     txt
                     Fri Feb 07 09:32:58 GMT 2014
                     0xCE4AA0B8
                     generationID_1879581046
                  
                  
                     ./chipscope_vio_fifo.cdc
                     unknown
                     Fri Feb 07 09:33:59 GMT 2014
                     0x4CA21057
                     generationID_1879581046
                  
                  
                     ./chipscope_vio_fifo.constraints/chipscope_vio_fifo.ucf
                     ucf
                     Fri Feb 07 09:33:59 GMT 2014
                     0x46D4F328
                     generationID_1879581046
                  
                  
                     ./chipscope_vio_fifo.constraints/chipscope_vio_fifo.xdc
                     xdc
                     Fri Feb 07 09:33:59 GMT 2014
                     0xC2D11607
                     generationID_1879581046
                  
                  
                     ./chipscope_vio_fifo.ngc
                     ngc
                     Fri Feb 07 09:33:57 GMT 2014
                     0xD2121D98
                     generationID_1879581046
                  
                  
                     ./chipscope_vio_fifo.ucf
                     ignore
                     ucf
                     Fri Feb 07 09:33:59 GMT 2014
                     0x46D4F328
                     generationID_1879581046
                  
                  
                     ./chipscope_vio_fifo.v
                     verilog
                     verilogSynthesis
                     Fri Feb 07 09:33:59 GMT 2014
                     0x81491EFF
                     generationID_1879581046
                  
                  
                     ./chipscope_vio_fifo.veo
                     veo
                     Fri Feb 07 09:33:59 GMT 2014
                     0x9DE1BF59
                     generationID_1879581046
                  
                  
                     ./chipscope_vio_fifo.xdc
                     ignore
                     xdc
                     Fri Feb 07 09:33:59 GMT 2014
                     0xC2D11607
                     generationID_1879581046
                  
                  
                     ./chipscope_vio_fifo_xmdf.tcl
                     tcl
                     Fri Feb 07 09:32:58 GMT 2014
                     0x136E503B
                     generationID_1879581046
                  
               
               
                  instantiation_template_generator
               
               
                  asy_generator
                  
                     ./chipscope_vio_fifo.asy
                     asy
                     Fri Feb 07 09:33:59 GMT 2014
                     0x42C0F37B
                     generationID_1879581046
                  
               
               
                  xmdf_generator
               
               
                  ise_generator
                  
                     ./chipscope_vio_fifo.gise
                     ignore
                     gise
                     Fri Feb 07 09:34:07 GMT 2014
                     0xE46738AE
                     generationID_1879581046
                  
                  
                     ./chipscope_vio_fifo.xise
                     ignore
                     xise
                     Fri Feb 07 09:34:07 GMT 2014
                     0x0BED329B
                     generationID_1879581046
                  
               
               
                  deliver_readme_generator
                  
                     ./chipscope_vio_fifo_readme.txt
                     ignore
                     txtReadme
                     txt
                     Fri Feb 07 09:34:07 GMT 2014
                     0xEA5F9500
                     generationID_1879581046
                  
               
               
                  flist_generator
                  
                     ./chipscope_vio_fifo_flist.txt
                     ignore
                     txtFlist
                     txt
                     Fri Feb 07 09:34:07 GMT 2014
                     0x2E57030C
                     generationID_1879581046
                  
               
               
                  view_readme_generator
               
            
         
      
      
         chipscope_vio_mask
         
         
            chipscope_vio_mask
            8
            40
            false
            false
            external
            false
            8
            true
            8
            false
            true
         
         
            
               
                  coregen
                  ./
                  ./tmp/
                  ./tmp/_cg/
               
               
                  xc7z020
                  zynq
                  clg400
                  -2
               
               
                  BusFormatAngleBracketNotRipped
                  Verilog
                  true
                  Other
                  false
                  false
                  false
                  Ngc
                  false
               
               
                  Structural
                  Verilog
                  false
               
               
                  2012-07-21+03:12
               
            
         
      
      
         chipscope_vio_trig
         
         
            chipscope_vio_trig
            8
            82
            false
            false
            external
            false
            8
            true
            8
            false
            true
         
         
            
               
                  coregen
                  ./
                  ./tmp/
                  ./tmp/_cg/
               
               
                  xc7z020
                  zynq
                  clg400
                  -2
               
               
                  BusFormatAngleBracketNotRipped
                  Verilog
                  true
                  Other
                  false
                  false
                  false
                  Ngc
                  false
               
               
                  Structural
                  Verilog
                  false
               
               
                  2012-10-12+23:08
               
            
         
      
      
         scfifo
         
         
            scfifo
            Common_Clock_Block_RAM
            2
            2
            Native
            Standard_FIFO
            98
            1024
            98
            1024
            false
            false
            true
            true
            Asynchronous_Reset
            1
            true
            0
            false
            false
            false
            Active_High
            false
            Active_High
            false
            Active_High
            false
            Active_High
            false
            false
            false
            true
            10
            false
            10
            false
            10
            false
            1
            1
            No_Programmable_Full_Threshold
            1022
            1021
            No_Programmable_Empty_Threshold
            2
            3
            AXI4_Stream
            Common_Clock
            false
            Slave_Interface_Clock_Enable
            false
            false
            4
            32
            64
            false
            1
            false
            1
            false
            1
            false
            1
            false
            1
            false
            64
            false
            8
            false
            4
            false
            4
            true
            false
            false
            4
            false
            4
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            16
            false
            No_Programmable_Full_Threshold
            1023
            No_Programmable_Empty_Threshold
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            1024
            false
            No_Programmable_Full_Threshold
            1023
            No_Programmable_Empty_Threshold
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            16
            false
            No_Programmable_Full_Threshold
            1023
            No_Programmable_Empty_Threshold
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            16
            false
            No_Programmable_Full_Threshold
            1023
            No_Programmable_Empty_Threshold
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            1024
            false
            No_Programmable_Full_Threshold
            1023
            No_Programmable_Empty_Threshold
            1022
            FIFO
            Common_Clock_Block_RAM
            Data_FIFO
            false
            false
            false
            1024
            false
            No_Programmable_Full_Threshold
            1023
            No_Programmable_Empty_Threshold
            1022
            Fully_Registered
            Fully_Registered
            Fully_Registered
            Fully_Registered
            Fully_Registered
            Fully_Registered
            false
            Active_High
            false
            Active_High
            false
            false
            false
            false
            false
         
         
            
               
                  coregen
                  ./
                  ./tmp/
                  ./tmp/_cg/
               
               
                  xc7z020
                  zynq
                  clg400
                  -2
               
               
                  BusFormatAngleBracketNotRipped
                  Verilog
                  true
                  Other
                  false
                  false
                  false
                  Ngc
                  false
               
               
                  Behavioral
                  Verilog
                  false
               
               
                  2012-06-23+13:35
               
            
         
      
   
   
      
         
            coregen
            ./
            ./tmp/
            ./tmp/_cg/
         
         
            xc7z020
            zynq
            clg400
            -2
         
         
            BusFormatAngleBracketNotRipped
            Verilog
            true
            Other
            false
            false
            false
            Ngc
            false
         
         
            Behavioral
            Verilog
            false
         
      
   

 

Line No.	Rev	Author	Line
1	18	ash_riple
2
3			`xilinx.com`
4			`project`
5			`coregen`
6			`1.0`
7
8
9			`chipscope_icon`
10
11
12			`chipscope_icon`
13			`false`
14			`3`
15			`true`
16			`external`
17			`false`
18			`false`
19			`USER1`
20			`false`
21
22
23
24
25			`coregen`
26			`./`
27			`./tmp/`
28			`./tmp/_cg/`
29
30
31			`xc7z020`
32			`zynq`
33			`clg400`
34			`-2`
35
36
37			`BusFormatAngleBracketNotRipped`
38			`Verilog`
39			`true`
40			`Other`
41			`false`
42			`false`
43			`false`
44			`Ngc`
45			`false`
46
47
48			`Behavioral`
49			`Verilog`
50			`false`
51
52
53			`2012-07-21+03:11`
54
55
56
57
58
59			`chipscope_vio_fifo`
60
61
62			`chipscope_vio_fifo`
63	20	ash_riple	`108`
64	18	ash_riple	`2`
65			`false`
66			`false`
67			`external`
68			`false`
69			`8`
70			`true`
71			`8`
72			`true`
73			`true`
74			`8`
75			`1`
76			`8`
77			`1`
78			`2`
79			`2`
80			`0`
81	20	ash_riple	`108`
82	18	ash_riple	`chipscope_vio_fifo`
83			`true`
84	20	ash_riple	`Component_Name=chipscope_vio_fifo;Enable_Synchronous_Input_Port=true;Enable_Synchronous_Output_Port=true;Enable_Asynchronous_Input_Port=false;Enable_Asynchronous_Output_Port=false;Synchronous_Input_Port_Width=108;Synchronous_Output_Port_Width=2;Asynchronous_Input_Port_Width=8;Asynchronous_Output_Port_Width=8;Invert_Clock_Input=false`
85	18	ash_riple	`external`
86			`0`
87			`0`
88			`1`
89
90
91
92
93			`coregen`
94			`./`
95			`./tmp/`
96			`./tmp/_cg/`
97
98
99			`xc7z020`
100			`zynq`
101			`clg400`
102			`-2`
103
104
105			`BusFormatAngleBracketNotRipped`
106			`Verilog`
107			`true`
108			`Other`
109			`false`
110			`false`
111			`false`
112			`Ngc`
113			`false`
114
115
116			`Structural`
117			`Verilog`
118			`false`
119
120
121	20	ash_riple	`2012-10-12+23:08`
122	18	ash_riple
123
124
125
126			`customization_generator`
127
128
129			`model_parameter_resolution_generator`
130
131
132			`ip_xco_generator`
133
134			`./chipscope_vio_fifo.xco`
135			`xco`
136	20	ash_riple	`Fri Feb 07 09:32:54 GMT 2014`
137			`0x724012F7`
138			`generationID_1879581046`
139	18	ash_riple
140
141
142			`ngc_netlist_generator`
143
144			`./chipscope_vio_fifo/example_design/chipscope_vio_fifo_bb_lib.v`
145			`ignore`
146			`verilogSynthesis`
147	20	ash_riple	`Fri Feb 07 09:32:54 GMT 2014`
148			`0xEC2F0FB0`
149			`generationID_1879581046`
150	18	ash_riple
151
152			`./chipscope_vio_fifo/example_design/example_chipscope_vio_fifo.ucf`
153			`ignore`
154			`ucf`
155	20	ash_riple	`Fri Feb 07 09:32:57 GMT 2014`
156	18	ash_riple	`0x1390C322`
157	20	ash_riple	`generationID_1879581046`
158	18	ash_riple
159
160			`./chipscope_vio_fifo/example_design/example_chipscope_vio_fifo.v`
161			`ignore`
162			`verilogSynthesis`
163	20	ash_riple	`Fri Feb 07 09:32:56 GMT 2014`
164			`0x8DB35830`
165			`generationID_1879581046`
166	18	ash_riple
167
168			`./chipscope_vio_fifo/example_design/example_chipscope_vio_fifo.xdc`
169			`ignore`
170			`xdc`
171	20	ash_riple	`Fri Feb 07 09:32:57 GMT 2014`
172			`0x938BE115`
173			`generationID_1879581046`
174	18	ash_riple
175
176			`./chipscope_vio_fifo/implement/chipscope_icon.xco`
177			`ignore`
178			`xco`
179	20	ash_riple	`Fri Feb 07 09:32:55 GMT 2014`
180	18	ash_riple	`0x1FF80BFB`
181	20	ash_riple	`generationID_1879581046`
182	18	ash_riple
183
184			`./chipscope_vio_fifo/implement/coregen.cgp`
185			`ignore`
186			`unknown`
187	20	ash_riple	`Fri Feb 07 09:32:55 GMT 2014`
188	18	ash_riple	`0x940C30DF`
189	20	ash_riple	`generationID_1879581046`
190	18	ash_riple
191
192			`./chipscope_vio_fifo/implement/example_chipscope_vio_fifo.prj`
193			`ignore`
194			`unknown`
195	20	ash_riple	`Fri Feb 07 09:32:56 GMT 2014`
196	18	ash_riple	`0xAE724F77`
197	20	ash_riple	`generationID_1879581046`
198	18	ash_riple
199
200			`./chipscope_vio_fifo/implement/example_chipscope_vio_fifo.xst`
201			`ignore`
202			`unknown`
203	20	ash_riple	`Fri Feb 07 09:32:58 GMT 2014`
204	18	ash_riple	`0xEBBE356D`
205	20	ash_riple	`generationID_1879581046`
206	18	ash_riple
207
208			`./chipscope_vio_fifo/implement/ise_implement.bat`
209			`ignore`
210			`unknown`
211	20	ash_riple	`Fri Feb 07 09:32:55 GMT 2014`
212	18	ash_riple	`0xEE86AB45`
213	20	ash_riple	`generationID_1879581046`
214	18	ash_riple
215
216			`./chipscope_vio_fifo/implement/ise_implement.sh`
217			`ignore`
218			`unknown`
219	20	ash_riple	`Fri Feb 07 09:32:58 GMT 2014`
220	18	ash_riple	`0x32780610`
221	20	ash_riple	`generationID_1879581046`
222	18	ash_riple
223
224			`./chipscope_vio_fifo/implement/pa_ise_implement.tcl`
225			`ignore`
226			`tcl`
227	20	ash_riple	`Fri Feb 07 09:32:56 GMT 2014`
228	18	ash_riple	`0xC8D9F8F9`
229	20	ash_riple	`generationID_1879581046`
230	18	ash_riple
231
232			`./chipscope_vio_fifo/implement/rdi_implement.tcl`
233			`ignore`
234			`tcl`
235	20	ash_riple	`Fri Feb 07 09:32:57 GMT 2014`
236	18	ash_riple	`0xBD351EB6`
237	20	ash_riple	`generationID_1879581046`
238	18	ash_riple
239
240			`./chipscope_vio_fifo/implement/v_rdi_implement.tcl`
241			`ignore`
242			`tcl`
243	20	ash_riple	`Fri Feb 07 09:32:58 GMT 2014`
244	18	ash_riple	`0x74FFDD3B`
245	20	ash_riple	`generationID_1879581046`
246	18	ash_riple
247
248			`./chipscope_vio_fifo/read_me.txt`
249			`ignore`
250			`txt`
251	20	ash_riple	`Fri Feb 07 09:32:58 GMT 2014`
252			`0xCE4AA0B8`
253			`generationID_1879581046`
254	18	ash_riple
255
256			`./chipscope_vio_fifo.cdc`
257			`unknown`
258	20	ash_riple	`Fri Feb 07 09:33:59 GMT 2014`
259			`0x4CA21057`
260			`generationID_1879581046`
261	18	ash_riple
262
263			`./chipscope_vio_fifo.constraints/chipscope_vio_fifo.ucf`
264			`ucf`
265	20	ash_riple	`Fri Feb 07 09:33:59 GMT 2014`
266	18	ash_riple	`0x46D4F328`
267	20	ash_riple	`generationID_1879581046`
268	18	ash_riple
269
270			`./chipscope_vio_fifo.constraints/chipscope_vio_fifo.xdc`
271			`xdc`
272	20	ash_riple	`Fri Feb 07 09:33:59 GMT 2014`
273	18	ash_riple	`0xC2D11607`
274	20	ash_riple	`generationID_1879581046`
275	18	ash_riple
276
277			`./chipscope_vio_fifo.ngc`
278			`ngc`
279	20	ash_riple	`Fri Feb 07 09:33:57 GMT 2014`
280			`0xD2121D98`
281			`generationID_1879581046`
282	18	ash_riple
283
284			`./chipscope_vio_fifo.ucf`
285			`ignore`
286			`ucf`
287	20	ash_riple	`Fri Feb 07 09:33:59 GMT 2014`
288	18	ash_riple	`0x46D4F328`
289	20	ash_riple	`generationID_1879581046`
290	18	ash_riple
291
292			`./chipscope_vio_fifo.v`
293			`verilog`
294			`verilogSynthesis`
295	20	ash_riple	`Fri Feb 07 09:33:59 GMT 2014`
296			`0x81491EFF`
297			`generationID_1879581046`
298	18	ash_riple
299
300			`./chipscope_vio_fifo.veo`
301			`veo`
302	20	ash_riple	`Fri Feb 07 09:33:59 GMT 2014`
303			`0x9DE1BF59`
304			`generationID_1879581046`
305	18	ash_riple
306
307			`./chipscope_vio_fifo.xdc`
308			`ignore`
309			`xdc`
310	20	ash_riple	`Fri Feb 07 09:33:59 GMT 2014`
311	18	ash_riple	`0xC2D11607`
312	20	ash_riple	`generationID_1879581046`
313	18	ash_riple
314
315			`./chipscope_vio_fifo_xmdf.tcl`
316			`tcl`
317	20	ash_riple	`Fri Feb 07 09:32:58 GMT 2014`
318	18	ash_riple	`0x136E503B`
319	20	ash_riple	`generationID_1879581046`
320	18	ash_riple
321
322
323			`instantiation_template_generator`
324
325
326			`asy_generator`
327
328			`./chipscope_vio_fifo.asy`
329			`asy`
330	20	ash_riple	`Fri Feb 07 09:33:59 GMT 2014`
331			`0x42C0F37B`
332			`generationID_1879581046`
333	18	ash_riple
334
335
336			`xmdf_generator`
337
338
339			`ise_generator`
340
341			`./chipscope_vio_fifo.gise`
342			`ignore`
343			`gise`
344	20	ash_riple	`Fri Feb 07 09:34:07 GMT 2014`
345	18	ash_riple	`0xE46738AE`
346	20	ash_riple	`generationID_1879581046`
347	18	ash_riple
348
349			`./chipscope_vio_fifo.xise`
350			`ignore`
351			`xise`
352	20	ash_riple	`Fri Feb 07 09:34:07 GMT 2014`
353			`0x0BED329B`
354			`generationID_1879581046`
355	18	ash_riple
356
357
358			`deliver_readme_generator`
359
360			`./chipscope_vio_fifo_readme.txt`
361			`ignore`
362			`txtReadme`
363			`txt`
364	20	ash_riple	`Fri Feb 07 09:34:07 GMT 2014`
365			`0xEA5F9500`
366			`generationID_1879581046`
367	18	ash_riple
368
369
370			`flist_generator`
371
372			`./chipscope_vio_fifo_flist.txt`
373			`ignore`
374			`txtFlist`
375			`txt`
376	20	ash_riple	`Fri Feb 07 09:34:07 GMT 2014`
377	18	ash_riple	`0x2E57030C`
378	20	ash_riple	`generationID_1879581046`
379	18	ash_riple
380
381
382			`view_readme_generator`
383
384
385
386
387
388			`chipscope_vio_mask`
389
390
391			`chipscope_vio_mask`
392			`8`
393			`40`
394			`false`
395			`false`
396			`external`
397			`false`
398			`8`
399			`true`
400			`8`
401			`false`
402			`true`
403
404
405
406
407			`coregen`
408			`./`
409			`./tmp/`
410			`./tmp/_cg/`
411
412
413			`xc7z020`
414			`zynq`
415			`clg400`
416			`-2`
417
418
419			`BusFormatAngleBracketNotRipped`
420			`Verilog`
421			`true`
422			`Other`
423			`false`
424			`false`
425			`false`
426			`Ngc`
427			`false`
428
429
430			`Structural`
431			`Verilog`
432			`false`
433
434
435			`2012-07-21+03:12`
436
437
438
439
440
441			`chipscope_vio_trig`
442
443
444			`chipscope_vio_trig`
445			`8`
446	20	ash_riple	`82`
447	18	ash_riple	`false`
448			`false`
449			`external`
450			`false`
451			`8`
452			`true`
453			`8`
454			`false`
455			`true`
456
457
458
459
460			`coregen`
461			`./`
462			`./tmp/`
463			`./tmp/_cg/`
464
465
466			`xc7z020`
467			`zynq`
468			`clg400`
469			`-2`
470
471
472			`BusFormatAngleBracketNotRipped`
473			`Verilog`
474			`true`
475			`Other`
476			`false`
477			`false`
478			`false`
479			`Ngc`
480			`false`
481
482
483			`Structural`
484			`Verilog`
485			`false`
486
487
488	20	ash_riple	`2012-10-12+23:08`
489	18	ash_riple
490
491
492
493
494			`scfifo`
495
496
497			`scfifo`
498			`Common_Clock_Block_RAM`
499			`2`
500			`2`

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