OpenCores
URL https://opencores.org/ocsvn/bustap-jtag/bustap-jtag/trunk

Subversion Repositories bustap-jtag

[/] [bustap-jtag/] [trunk/] [rtl/] [xilinx/] [vivado_ip/] [component.xml] - Blame information for rev 25

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Line No. Rev Author Line
1 25 ash_riple
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  OpenCores
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  user
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  bustap_jtag_v1_0
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  1.0
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      s00_axi
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            AWADDR
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            s00_axi_awaddr
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            AWPROT
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            s00_axi_awprot
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            AWVALID
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            s00_axi_awvalid
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            AWREADY
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            s00_axi_awready
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            WDATA
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            s00_axi_wdata
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            WSTRB
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            s00_axi_wstrb
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            WVALID
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            s00_axi_wvalid
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            WREADY
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            s00_axi_wready
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            BRESP
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            s00_axi_bresp
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            BVALID
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            s00_axi_bvalid
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            BREADY
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            s00_axi_bready
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            ARADDR
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            s00_axi_araddr
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            ARPROT
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            s00_axi_arprot
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            ARVALID
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            s00_axi_arvalid
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            ARREADY
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            RDATA
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            s00_axi_rdata
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            RRESP
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            s00_axi_rresp
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            RVALID
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            s00_axi_rvalid
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            RREADY
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            s00_axi_rready
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      m00_axi
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            AWADDR
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            m00_axi_awaddr
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            AWPROT
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            m00_axi_awprot
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            AWVALID
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            m00_axi_awvalid
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            AWREADY
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            m00_axi_awready
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            WDATA
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            m00_axi_wdata
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            WSTRB
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            m00_axi_wstrb
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            WVALID
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            m00_axi_wvalid
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            WREADY
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            m00_axi_wready
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            BRESP
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            m00_axi_bresp
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            BVALID
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            m00_axi_bvalid
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            BREADY
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            m00_axi_bready
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            ARADDR
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            m00_axi_araddr
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            ARPROT
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            m00_axi_arprot
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            ARVALID
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            m00_axi_arvalid
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            ARREADY
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            m00_axi_arready
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            RDATA
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            m00_axi_rdata
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            RRESP
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            m00_axi_rresp
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            RVALID
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            m00_axi_rvalid
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            RREADY
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            m00_axi_rready
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          FREQ_HZ
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      s00_axi_signal_clock
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            CLK
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            s00_axi_aclk
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          ASSOCIATED_BUSIF
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          s00_axi
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      s00_axi_signal_reset
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            RST
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            s00_axi_aresetn
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          POLARITY
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          ACTIVE_LOW
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      m00_axi_signal_clock
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            CLK
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            m00_axi_aclk
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          ASSOCIATED_BUSIF
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          m00_axi
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      m00_axi_signal_reset
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            RST
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            m00_axi_aresetn
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          POLARITY
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          ACTIVE_LOW
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      s00_axi
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        reg0
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        0
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        16
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        32
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        register
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        xilinx_verilogsynthesis
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        Verilog Synthesis
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        verilogSource:vivado.xilinx.com:synthesis
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        verilog
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        bustap_jtag_v1_0
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          xilinx_verilogsynthesis_view_fileset
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            viewChecksum
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            bbdb8244
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        xilinx_verilogbehavioralsimulation
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        Verilog Simulation
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        verilogSource:vivado.xilinx.com:simulation
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        verilog
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        bustap_jtag_v1_0
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          xilinx_verilogbehavioralsimulation_view_fileset
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            viewChecksum
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            eae1c910
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        xilinx_xpgui
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        UI Layout
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        :vivado.xilinx.com:xgui.ui
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          xilinx_xpgui_view_fileset
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            viewChecksum
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            593ee5d6
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        xilinx_utilityxitfiles
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        Utility XIT/TTCL
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        :vivado.xilinx.com:xit.util
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          xilinx_utilityxitfiles_view_fileset
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            viewChecksum
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            698ee63a
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        s00_axi_aclk
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          in
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              wire
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              xilinx_verilogsynthesis
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              xilinx_verilogbehavioralsimulation
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        s00_axi_aresetn
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          in
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              wire
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              xilinx_verilogsynthesis
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              xilinx_verilogbehavioralsimulation
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        s00_axi_awaddr
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          in
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            3
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            0
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              wire
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              xilinx_verilogsynthesis
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              xilinx_verilogbehavioralsimulation
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            0
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        s00_axi_awprot
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          in
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            2
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            0
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              wire
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              xilinx_verilogsynthesis
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              xilinx_verilogbehavioralsimulation
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            0
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        s00_axi_awvalid
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          in
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              wire
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              xilinx_verilogsynthesis
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              xilinx_verilogbehavioralsimulation
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            0
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        s00_axi_awready
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          out
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              wire
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              xilinx_verilogsynthesis
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              xilinx_verilogbehavioralsimulation
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        s00_axi_wdata
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          in
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            31
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            0
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              wire
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              xilinx_verilogsynthesis
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              xilinx_verilogbehavioralsimulation
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            0
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        s00_axi_wstrb
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          in
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            3
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            0
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              wire
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              xilinx_verilogsynthesis
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              xilinx_verilogbehavioralsimulation
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        s00_axi_wvalid
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          in
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              wire
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              xilinx_verilogsynthesis
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              xilinx_verilogbehavioralsimulation
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            0
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        s00_axi_wready
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          out
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              wire
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              xilinx_verilogsynthesis
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              xilinx_verilogbehavioralsimulation
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        s00_axi_bresp
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          out
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            1
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            0
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              wire
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              xilinx_verilogsynthesis
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              xilinx_verilogbehavioralsimulation
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        s00_axi_bvalid
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          out
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              wire
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              xilinx_verilogsynthesis
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              xilinx_verilogbehavioralsimulation
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        s00_axi_bready
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          in
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              wire
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              xilinx_verilogsynthesis
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              xilinx_verilogbehavioralsimulation
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            0
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        s00_axi_araddr
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          in
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            3
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            0
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              wire
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              xilinx_verilogsynthesis
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              xilinx_verilogbehavioralsimulation
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            0
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        s00_axi_arprot
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          in
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            0
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              wire
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              xilinx_verilogsynthesis
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              xilinx_verilogbehavioralsimulation
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            0
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        s00_axi_arvalid
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          in
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              wire
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              xilinx_verilogsynthesis
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              xilinx_verilogbehavioralsimulation
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            0
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        s00_axi_arready
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          out
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              wire
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              xilinx_verilogsynthesis
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              xilinx_verilogbehavioralsimulation
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        s00_axi_rdata
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          out
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            31
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            0
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              wire
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              xilinx_verilogsynthesis
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              xilinx_verilogbehavioralsimulation
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        s00_axi_rresp
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          out
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            1
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            0
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              wire
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              xilinx_verilogsynthesis
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              xilinx_verilogbehavioralsimulation
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        s00_axi_rvalid
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          out
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              wire
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              xilinx_verilogsynthesis
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              xilinx_verilogbehavioralsimulation
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        s00_axi_rready
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          in
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              wire
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              xilinx_verilogsynthesis
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              xilinx_verilogbehavioralsimulation
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            0
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        m00_axi_aclk
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          in
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              wire
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              xilinx_verilogsynthesis
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              xilinx_verilogbehavioralsimulation
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        m00_axi_aresetn
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          in
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              wire
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              xilinx_verilogsynthesis
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              xilinx_verilogbehavioralsimulation
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        m00_axi_awaddr
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          out
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            3
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            0
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              wire
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              xilinx_verilogsynthesis
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              xilinx_verilogbehavioralsimulation
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        m00_axi_awprot
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          out
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            2
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            0
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              wire
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              xilinx_verilogsynthesis
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              xilinx_verilogbehavioralsimulation
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        m00_axi_awvalid
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          out
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              wire
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              xilinx_verilogsynthesis
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              xilinx_verilogbehavioralsimulation
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        m00_axi_awready
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          in
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              wire
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              xilinx_verilogsynthesis
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              xilinx_verilogbehavioralsimulation
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            0
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        m00_axi_wdata
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          out
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            0
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              wire
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              xilinx_verilogsynthesis
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              xilinx_verilogbehavioralsimulation
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        m00_axi_wstrb
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          out
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            0
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              wire
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              xilinx_verilogsynthesis
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              xilinx_verilogbehavioralsimulation
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        m00_axi_wvalid
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          out
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              wire
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              xilinx_verilogsynthesis
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              xilinx_verilogbehavioralsimulation
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        m00_axi_wready
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          in
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              wire
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              xilinx_verilogsynthesis
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              xilinx_verilogbehavioralsimulation
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            0
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        m00_axi_bresp
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          in
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            1
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            0
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              wire
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              xilinx_verilogsynthesis
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              xilinx_verilogbehavioralsimulation
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            0
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        m00_axi_bvalid
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          in
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              wire
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              xilinx_verilogsynthesis
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              xilinx_verilogbehavioralsimulation
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            0
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        m00_axi_bready
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          out
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              wire
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              xilinx_verilogsynthesis
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              xilinx_verilogbehavioralsimulation
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1038
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        m00_axi_araddr
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          out
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            3
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            0
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              wire
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              xilinx_verilogsynthesis
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              xilinx_verilogbehavioralsimulation
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        m00_axi_arprot
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          out
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            2
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            0
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              wire
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              xilinx_verilogsynthesis
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              xilinx_verilogbehavioralsimulation
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1073
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        m00_axi_arvalid
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          out
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1080
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              wire
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              xilinx_verilogsynthesis
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              xilinx_verilogbehavioralsimulation
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        m00_axi_arready
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          in
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              wire
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              xilinx_verilogsynthesis
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              xilinx_verilogbehavioralsimulation
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            0
1101
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1103
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        m00_axi_rdata
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          in
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            31
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            0
1111
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              wire
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              xilinx_verilogsynthesis
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              xilinx_verilogbehavioralsimulation
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            0
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1124
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        m00_axi_rresp
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          in
1128
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            1
1130 
            0
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              wire
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              xilinx_verilogsynthesis
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              xilinx_verilogbehavioralsimulation
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            0
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        m00_axi_rvalid
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          in
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              wire
1151 
              xilinx_verilogsynthesis
1152 
              xilinx_verilogbehavioralsimulation
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            0
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        m00_axi_rready
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          out
1164
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              wire
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              xilinx_verilogsynthesis
1168 
              xilinx_verilogbehavioralsimulation
1169
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        C_S00_AXI_DATA_WIDTH
1177 
        C S00 Axi Data Width
1178 
        32
1179
1180
1181 
        C_S00_AXI_ADDR_WIDTH
1182 
        C S00 Axi Addr Width
1183 
        4
1184
1185
1186 
        C_M00_AXI_DATA_WIDTH
1187 
        C M00 Axi Data Width
1188 
        32
1189
1190
1191 
        C_M00_AXI_ADDR_WIDTH
1192 
        C M00 Axi Addr Width
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        4
1194
1195
1196
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      choices_0
1200 
      ACTIVE_HIGH
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      ACTIVE_LOW
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      choices_1
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      ACTIVE_HIGH
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      ACTIVE_LOW
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      choices_2
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      ACTIVE_HIGH
1211 
      ACTIVE_LOW
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      choices_3
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      ACTIVE_HIGH
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      ACTIVE_LOW
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      choices_4
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      ACTIVE_HIGH
1221 
      ACTIVE_LOW
1222
1223
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      xilinx_verilogsynthesis_view_fileset
1227
1228 
        ../../xilinx/coregen/scfifo.v
1229 
        verilogSource
1230
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1232 
        ../../xilinx/coregen/scfifo.ngc
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        ngc
1234 
        core
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        ../../xilinx/coregen/chipscope_vio_trig.v
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        verilogSource
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        ../../xilinx/coregen/chipscope_vio_trig.ngc
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        ngc
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        core
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        ../../xilinx/coregen/chipscope_vio_mask.v
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        verilogSource
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        ../../xilinx/coregen/chipscope_vio_mask.ngc
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        ngc
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        core
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        ../../xilinx/coregen/chipscope_vio_fifo.v
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        verilogSource
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        ../../xilinx/coregen/chipscope_vio_fifo.ngc
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        ngc
1261 
        core
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        ../../xilinx/coregen/chipscope_icon.v
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        verilogSource
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1268 
        ../../xilinx/coregen/chipscope_icon.ngc
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        ngc
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        core
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        ../../xilinx/chipscope_vio_addr_mask.v
1274 
        verilogSource
1275
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        ../../xilinx/chipscope_vio_adda_trig.v
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        verilogSource
1279
1280
1281 
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