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[/] [bw_tiff_compression/] [trunk/] [var_width_RAM.vhd] - Blame information for rev 12

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----------------------------------------------------------------------------------
-- Company:        
-- Engineer:       Aart Mulder
-- 
-- Create Date:    15:02:11 12/13/2012 
-- Design Name:    Tiff compression and transmission
-- Module Name:    var_width_RAM - Behavioral 
-- Project Name:   CCITT4
--
-- Revision: 
-- Revision 0.01 - File Created
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
 
entity var_width_RAM is
        Generic (
                MEM_SIZE_G        : integer := 1024;
                MEM_INDEX_WIDTH_G : integer := 10;
                DATA_WIDTH_G     : integer := 8
        );
        Port (
                reset_i   : in  STD_LOGIC;
                clk_i     : in  STD_LOGIC;
                d1_i      : in  STD_LOGIC_VECTOR (DATA_WIDTH_G-1 downto 0);
                wr1_i   : in  STD_LOGIC;
                d2_i      : in  STD_LOGIC_VECTOR (DATA_WIDTH_G-1 downto 0);
                wr2_i   : in  STD_LOGIC;
                d3_i      : in  STD_LOGIC_VECTOR (DATA_WIDTH_G-1 downto 0);
                wr3_i   : in  STD_LOGIC;
                d4_i      : in  STD_LOGIC_VECTOR (DATA_WIDTH_G-1 downto 0);
                wr4_i   : in  STD_LOGIC;
                rd_addr_i : in  STD_LOGIC_VECTOR (MEM_INDEX_WIDTH_G-1 downto 0);
                d_o       : out STD_LOGIC_VECTOR (DATA_WIDTH_G-1 downto 0);
                used_o    : out unsigned (MEM_INDEX_WIDTH_G-1 downto 0)
        );
end var_width_RAM;
 
architecture Behavioral of var_width_RAM is
        signal rd1, rd2, rd3, rd4, wr1, wr2, wr3, wr4 : std_logic := '0';
        signal rd_addr1, rd_addr2, rd_addr3, rd_addr4, wr_addr1, wr_addr2, wr_addr3, wr_addr4 : std_logic_vector(MEM_INDEX_WIDTH_G-3 downto 0) := (others => '0');
        signal d1_in, d2_in, d3_in, d4_in, d1_out, d2_out, d3_out, d4_out : std_logic_vector(DATA_WIDTH_G-1 downto 0) := (others => '0');
        signal mux_sel : unsigned(1 downto 0) := (others => '0');
begin
        RAM_ins1 : entity work.MyRAM
        generic map(
                DATA_WIDTH_G => DATA_WIDTH_G,
                MEMORY_SIZE_G => MEM_SIZE_G/4,
                MEMORY_ADDRESS_WIDTH_G  => MEM_INDEX_WIDTH_G-2,
                BUFFER_OUTPUT_G => true
        )
        port map(
                clk => clk_i,
                en => '1',
                rd => rd1,
                wr => wr1,
                rd_addr => rd_addr1,
                wr_addr => wr_addr1,
                Data_in => d1_in,
                Data_out => d1_out
        );
        rd_addr1 <= rd_addr_i(MEM_INDEX_WIDTH_G-1 downto 2);
        rd1 <= (not rd_addr_i(1)) and (not rd_addr_i(0));
 
        RAM_ins2 : entity work.MyRAM
        generic map(
                DATA_WIDTH_G => DATA_WIDTH_G,
                MEMORY_SIZE_G => MEM_SIZE_G/4,
                MEMORY_ADDRESS_WIDTH_G  => MEM_INDEX_WIDTH_G-2,
                BUFFER_OUTPUT_G => true
        )
        port map(
                clk => clk_i,
                en => '1',
                rd => rd2,
                wr => wr2,
                rd_addr => rd_addr2,
                wr_addr => wr_addr2,
                Data_in => d2_in,
                Data_out => d2_out
        );
        rd_addr2 <= rd_addr_i(MEM_INDEX_WIDTH_G-1 downto 2);
        rd2 <= (not rd_addr_i(1)) and (rd_addr_i(0));
 
        RAM_ins3 : entity work.MyRAM
        generic map(
                DATA_WIDTH_G => DATA_WIDTH_G,
                MEMORY_SIZE_G => MEM_SIZE_G/4,
                MEMORY_ADDRESS_WIDTH_G  => MEM_INDEX_WIDTH_G-2,
                BUFFER_OUTPUT_G => true
        )
        port map(
                clk => clk_i,
                en => '1',
                rd => rd3,
                wr => wr3,
                rd_addr => rd_addr3,
                wr_addr => wr_addr3,
                Data_in => d3_in,
                Data_out => d3_out
        );
        rd_addr3 <= rd_addr_i(MEM_INDEX_WIDTH_G-1 downto 2);
        rd3 <= (rd_addr_i(1)) and (not rd_addr_i(0));
 
        RAM_ins4 : entity work.MyRAM
        generic map(
                DATA_WIDTH_G => DATA_WIDTH_G,
                MEMORY_SIZE_G => MEM_SIZE_G/4,
                MEMORY_ADDRESS_WIDTH_G  => MEM_INDEX_WIDTH_G-2,
                BUFFER_OUTPUT_G => true
        )
        port map(
                clk => clk_i,
                en => '1',
                rd => rd4,
                wr => wr4,
                rd_addr => rd_addr4,
                wr_addr => wr_addr4,
                Data_in => d4_in,
                Data_out => d4_out
        );
        rd_addr4 <= rd_addr_i(MEM_INDEX_WIDTH_G-1 downto 2);
        rd4 <= (rd_addr_i(1)) and (rd_addr_i(0));
 
        --Multiplexer that selects the RAM output data
        d_o <= d1_out when rd_addr_i(1 downto 0) = "00"
                        else d2_out when rd_addr_i(1 downto 0) = "01"
                        else d3_out when rd_addr_i(1 downto 0) = "10"
                        else d4_out when rd_addr_i(1 downto 0) = "11";
 
        --The multiplexer selection counter
        mux_sel_cnt_process : process(clk_i)
        begin
                if clk_i'event and clk_i = '0' then
                        -- "0000" => 0
                        -- "0001" => 1
                        -- "0011" => 2 
                        -- "0111" => 3
                        -- "1111" => 4 = 0
 
                        if reset_i = '1' then
                                mux_sel <= (others => '0');
                        elsif    wr4_i = '0' and wr3_i = '0' and wr2_i = '0' and wr1_i = '1' then
                                mux_sel <= mux_sel - to_unsigned(1,2);
                        elsif wr4_i = '0' and wr3_i = '0' and wr2_i = '1' and wr1_i = '1' then
                                mux_sel <= mux_sel - to_unsigned(2,2);
                        elsif wr4_i = '0' and wr3_i = '1' and wr2_i = '1' and wr1_i = '1' then
                                mux_sel <= mux_sel - to_unsigned(3,2);
                        else
                                mux_sel <= mux_sel - to_unsigned(0,2);
                        end if;
                end if;
        end process mux_sel_cnt_process;
 
        --This process controls the read addresses, i.e. counting up and reseting.
        rd_addr_cnt_process : process(clk_i)
        begin
                if clk_i'event and clk_i = '1' then
                        if reset_i = '1' then
                                wr_addr1 <= (others => '0');
                                wr_addr2 <= (others => '0');
                                wr_addr3 <= (others => '0');
                                wr_addr4 <= (others => '0');
                        else
                                if wr1 = '1' then
                                        wr_addr1 <= std_logic_vector(unsigned(wr_addr1) + to_unsigned(1, MEM_INDEX_WIDTH_G - 3));
                                end if;
                                if wr2 = '1' then
                                        wr_addr2 <= std_logic_vector(unsigned(wr_addr2) + to_unsigned(1, MEM_INDEX_WIDTH_G - 3));
                                end if;
                                if wr3 = '1' then
                                        wr_addr3 <= std_logic_vector(unsigned(wr_addr3) + to_unsigned(1, MEM_INDEX_WIDTH_G - 3));
                                end if;
                                if wr4 = '1' then
                                        wr_addr4 <= std_logic_vector(unsigned(wr_addr4) + to_unsigned(1, MEM_INDEX_WIDTH_G - 3));
                                end if;
                        end if;
                end if;
        end process rd_addr_cnt_process;
 
        --Multiplexer 1(input to RAM 1)
        mux1_process : process(clk_i)
        begin
                if clk_i'event and clk_i = '0' then
                        if (mux_sel + to_unsigned(0,2)) = to_unsigned(0,2) then
                                wr1 <= wr1_i;
                                d1_in <= d1_i;
                        elsif (mux_sel + to_unsigned(0,2)) = to_unsigned(1,2) then
                                wr1 <= wr2_i;
                                d1_in <= d2_i;
                        elsif (mux_sel + to_unsigned(0,2)) = to_unsigned(2,2) then
                                wr1 <= wr3_i;
                                d1_in <= d3_i;
                        elsif (mux_sel + to_unsigned(0,2)) = to_unsigned(3,2) then
                                wr1 <= wr4_i;
                                d1_in <= d4_i;
                        end if;
                end if;
        end process mux1_process;
 
        --Multiplexer 2(input to RAM 2)
        mux2_process : process(clk_i)
        begin
                if clk_i'event and clk_i = '0' then
                        if (mux_sel + to_unsigned(1,2)) = to_unsigned(0,2) then
                                wr2 <= wr1_i;
                                d2_in <= d1_i;
                        elsif (mux_sel + to_unsigned(1,2)) = to_unsigned(1,2) then
                                wr2 <= wr2_i;
                                d2_in <= d2_i;
                        elsif (mux_sel + to_unsigned(1,2)) = to_unsigned(2,2) then
                                wr2 <= wr3_i;
                                d2_in <= d3_i;
                        elsif (mux_sel + to_unsigned(1,2)) = to_unsigned(3,2) then
                                wr2 <= wr4_i;
                                d2_in <= d4_i;
                        end if;
                end if;
        end process mux2_process;
 
        --Multiplexer 3(input to RAM 3)
        mux3_process : process(clk_i)
        begin
                if clk_i'event and clk_i = '0' then
                        if (mux_sel + to_unsigned(2,2)) = to_unsigned(0,2) then
                                wr3 <= wr1_i;
                                d3_in <= d1_i;
                        elsif (mux_sel + to_unsigned(2,2)) = to_unsigned(1,2) then
                                wr3 <= wr2_i;
                                d3_in <= d2_i;
                        elsif (mux_sel + to_unsigned(2,2)) = to_unsigned(2,2) then
                                wr3 <= wr3_i;
                                d3_in <= d3_i;
                        elsif (mux_sel + to_unsigned(2,2)) = to_unsigned(3,2) then
                                wr3 <= wr4_i;
                                d3_in <= d4_i;
                        end if;
                end if;
        end process mux3_process;
 
        --Multiplexer 4(input to RAM 4)
        mux4_process : process(clk_i)
        begin
                if clk_i'event and clk_i = '0' then
                        if (mux_sel + to_unsigned(3,2)) = to_unsigned(0,2) then
                                wr4 <= wr1_i;
                                d4_in <= d1_i;
                        elsif (mux_sel + to_unsigned(3,2)) = to_unsigned(1,2) then
                                wr4 <= wr2_i;
                                d4_in <= d2_i;
                        elsif (mux_sel + to_unsigned(3,2)) = to_unsigned(2,2) then
                                wr4 <= wr3_i;
                                d4_in <= d3_i;
                        elsif (mux_sel + to_unsigned(3,2)) = to_unsigned(3,2) then
                                wr4 <= wr4_i;
                                d4_in <= d4_i;
                        end if;
                end if;
        end process mux4_process;
 
        used_o <= ("00" & unsigned(wr_addr1)) + ("00" & unsigned(wr_addr2)) + ("00" & unsigned(wr_addr3)) + ("00" & unsigned(wr_addr4));
 
end Behavioral;

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Subversion Repositories bw_tiff_compression

[/] [bw_tiff_compression/] [trunk/] [var_width_RAM.vhd] - Blame information for rev 12

Line No.	Rev	Author	Line
1	2	amulder	`----------------------------------------------------------------------------------`
2			`-- Company:`
3			`-- Engineer: Aart Mulder`
4			`--`
5			`-- Create Date: 15:02:11 12/13/2012`
6			`-- Design Name: Tiff compression and transmission`
7			`-- Module Name: var_width_RAM - Behavioral`
8			`-- Project Name: CCITT4`
9			`--`
10			`-- Revision:`
11			`-- Revision 0.01 - File Created`
12			`--`
13			`----------------------------------------------------------------------------------`
14			`library IEEE;`
15			`use IEEE.STD_LOGIC_1164.ALL;`
16			`use IEEE.NUMERIC_STD.ALL;`
17
18			`entity var_width_RAM is`
19			`Generic (`
20			`MEM_SIZE_G : integer := 1024;`
21			`MEM_INDEX_WIDTH_G : integer := 10;`
22			`DATA_WIDTH_G : integer := 8`
23			`);`
24			`Port (`
25			`reset_i : in STD_LOGIC;`
26			`clk_i : in STD_LOGIC;`
27			`d1_i : in STD_LOGIC_VECTOR (DATA_WIDTH_G-1 downto 0);`
28			`wr1_i : in STD_LOGIC;`
29			`d2_i : in STD_LOGIC_VECTOR (DATA_WIDTH_G-1 downto 0);`
30			`wr2_i : in STD_LOGIC;`
31			`d3_i : in STD_LOGIC_VECTOR (DATA_WIDTH_G-1 downto 0);`
32			`wr3_i : in STD_LOGIC;`
33			`d4_i : in STD_LOGIC_VECTOR (DATA_WIDTH_G-1 downto 0);`
34			`wr4_i : in STD_LOGIC;`
35			`rd_addr_i : in STD_LOGIC_VECTOR (MEM_INDEX_WIDTH_G-1 downto 0);`
36			`d_o : out STD_LOGIC_VECTOR (DATA_WIDTH_G-1 downto 0);`
37			`used_o : out unsigned (MEM_INDEX_WIDTH_G-1 downto 0)`
38			`);`
39			`end var_width_RAM;`
40
41			`architecture Behavioral of var_width_RAM is`
42			`signal rd1, rd2, rd3, rd4, wr1, wr2, wr3, wr4 : std_logic := '0';`
43			`signal rd_addr1, rd_addr2, rd_addr3, rd_addr4, wr_addr1, wr_addr2, wr_addr3, wr_addr4 : std_logic_vector(MEM_INDEX_WIDTH_G-3 downto 0) := (others => '0');`
44			`signal d1_in, d2_in, d3_in, d4_in, d1_out, d2_out, d3_out, d4_out : std_logic_vector(DATA_WIDTH_G-1 downto 0) := (others => '0');`
45			`signal mux_sel : unsigned(1 downto 0) := (others => '0');`
46			`begin`
47			`RAM_ins1 : entity work.MyRAM`
48			`generic map(`
49			`DATA_WIDTH_G => DATA_WIDTH_G,`
50			`MEMORY_SIZE_G => MEM_SIZE_G/4,`
51			`MEMORY_ADDRESS_WIDTH_G => MEM_INDEX_WIDTH_G-2,`
52			`BUFFER_OUTPUT_G => true`
53			`)`
54			`port map(`
55			`clk => clk_i,`
56			`en => '1',`
57			`rd => rd1,`
58			`wr => wr1,`
59			`rd_addr => rd_addr1,`
60			`wr_addr => wr_addr1,`
61			`Data_in => d1_in,`
62			`Data_out => d1_out`
63			`);`
64			`rd_addr1 <= rd_addr_i(MEM_INDEX_WIDTH_G-1 downto 2);`
65			`rd1 <= (not rd_addr_i(1)) and (not rd_addr_i(0));`
66
67			`RAM_ins2 : entity work.MyRAM`
68			`generic map(`
69			`DATA_WIDTH_G => DATA_WIDTH_G,`
70			`MEMORY_SIZE_G => MEM_SIZE_G/4,`
71			`MEMORY_ADDRESS_WIDTH_G => MEM_INDEX_WIDTH_G-2,`
72			`BUFFER_OUTPUT_G => true`
73			`)`
74			`port map(`
75			`clk => clk_i,`
76			`en => '1',`
77			`rd => rd2,`
78			`wr => wr2,`
79			`rd_addr => rd_addr2,`
80			`wr_addr => wr_addr2,`
81			`Data_in => d2_in,`
82			`Data_out => d2_out`
83			`);`
84			`rd_addr2 <= rd_addr_i(MEM_INDEX_WIDTH_G-1 downto 2);`
85			`rd2 <= (not rd_addr_i(1)) and (rd_addr_i(0));`
86
87			`RAM_ins3 : entity work.MyRAM`
88			`generic map(`
89			`DATA_WIDTH_G => DATA_WIDTH_G,`
90			`MEMORY_SIZE_G => MEM_SIZE_G/4,`
91			`MEMORY_ADDRESS_WIDTH_G => MEM_INDEX_WIDTH_G-2,`
92			`BUFFER_OUTPUT_G => true`
93			`)`
94			`port map(`
95			`clk => clk_i,`
96			`en => '1',`
97			`rd => rd3,`
98			`wr => wr3,`
99			`rd_addr => rd_addr3,`
100			`wr_addr => wr_addr3,`
101			`Data_in => d3_in,`
102			`Data_out => d3_out`
103			`);`
104			`rd_addr3 <= rd_addr_i(MEM_INDEX_WIDTH_G-1 downto 2);`
105			`rd3 <= (rd_addr_i(1)) and (not rd_addr_i(0));`
106
107			`RAM_ins4 : entity work.MyRAM`
108			`generic map(`
109			`DATA_WIDTH_G => DATA_WIDTH_G,`
110			`MEMORY_SIZE_G => MEM_SIZE_G/4,`
111			`MEMORY_ADDRESS_WIDTH_G => MEM_INDEX_WIDTH_G-2,`
112			`BUFFER_OUTPUT_G => true`
113			`)`
114			`port map(`
115			`clk => clk_i,`
116			`en => '1',`
117			`rd => rd4,`
118			`wr => wr4,`
119			`rd_addr => rd_addr4,`
120			`wr_addr => wr_addr4,`
121			`Data_in => d4_in,`
122			`Data_out => d4_out`
123			`);`
124			`rd_addr4 <= rd_addr_i(MEM_INDEX_WIDTH_G-1 downto 2);`
125			`rd4 <= (rd_addr_i(1)) and (rd_addr_i(0));`
126
127			`--Multiplexer that selects the RAM output data`
128			`d_o <= d1_out when rd_addr_i(1 downto 0) = "00"`
129			`else d2_out when rd_addr_i(1 downto 0) = "01"`
130			`else d3_out when rd_addr_i(1 downto 0) = "10"`
131			`else d4_out when rd_addr_i(1 downto 0) = "11";`
132
133			`--The multiplexer selection counter`
134			`mux_sel_cnt_process : process(clk_i)`
135			`begin`
136			`if clk_i'event and clk_i = '0' then`
137			`-- "0000" => 0`
138			`-- "0001" => 1`
139			`-- "0011" => 2`
140			`-- "0111" => 3`
141			`-- "1111" => 4 = 0`
142
143			`if reset_i = '1' then`
144			`mux_sel <= (others => '0');`
145			`elsif wr4_i = '0' and wr3_i = '0' and wr2_i = '0' and wr1_i = '1' then`
146			`mux_sel <= mux_sel - to_unsigned(1,2);`
147			`elsif wr4_i = '0' and wr3_i = '0' and wr2_i = '1' and wr1_i = '1' then`
148			`mux_sel <= mux_sel - to_unsigned(2,2);`
149			`elsif wr4_i = '0' and wr3_i = '1' and wr2_i = '1' and wr1_i = '1' then`
150			`mux_sel <= mux_sel - to_unsigned(3,2);`
151			`else`
152			`mux_sel <= mux_sel - to_unsigned(0,2);`
153			`end if;`
154			`end if;`
155			`end process mux_sel_cnt_process;`
156
157			`--This process controls the read addresses, i.e. counting up and reseting.`
158			`rd_addr_cnt_process : process(clk_i)`
159			`begin`
160			`if clk_i'event and clk_i = '1' then`
161			`if reset_i = '1' then`
162			`wr_addr1 <= (others => '0');`
163			`wr_addr2 <= (others => '0');`
164			`wr_addr3 <= (others => '0');`
165			`wr_addr4 <= (others => '0');`
166			`else`
167			`if wr1 = '1' then`
168			`wr_addr1 <= std_logic_vector(unsigned(wr_addr1) + to_unsigned(1, MEM_INDEX_WIDTH_G - 3));`
169			`end if;`
170			`if wr2 = '1' then`
171			`wr_addr2 <= std_logic_vector(unsigned(wr_addr2) + to_unsigned(1, MEM_INDEX_WIDTH_G - 3));`
172			`end if;`
173			`if wr3 = '1' then`
174			`wr_addr3 <= std_logic_vector(unsigned(wr_addr3) + to_unsigned(1, MEM_INDEX_WIDTH_G - 3));`
175			`end if;`
176			`if wr4 = '1' then`
177			`wr_addr4 <= std_logic_vector(unsigned(wr_addr4) + to_unsigned(1, MEM_INDEX_WIDTH_G - 3));`
178			`end if;`
179			`end if;`
180			`end if;`
181			`end process rd_addr_cnt_process;`
182
183			`--Multiplexer 1(input to RAM 1)`
184			`mux1_process : process(clk_i)`
185			`begin`
186			`if clk_i'event and clk_i = '0' then`
187			`if (mux_sel + to_unsigned(0,2)) = to_unsigned(0,2) then`
188			`wr1 <= wr1_i;`
189			`d1_in <= d1_i;`
190			`elsif (mux_sel + to_unsigned(0,2)) = to_unsigned(1,2) then`
191			`wr1 <= wr2_i;`
192			`d1_in <= d2_i;`
193			`elsif (mux_sel + to_unsigned(0,2)) = to_unsigned(2,2) then`
194			`wr1 <= wr3_i;`
195			`d1_in <= d3_i;`
196			`elsif (mux_sel + to_unsigned(0,2)) = to_unsigned(3,2) then`
197			`wr1 <= wr4_i;`
198			`d1_in <= d4_i;`
199			`end if;`
200			`end if;`
201			`end process mux1_process;`
202
203			`--Multiplexer 2(input to RAM 2)`
204			`mux2_process : process(clk_i)`
205			`begin`
206			`if clk_i'event and clk_i = '0' then`
207			`if (mux_sel + to_unsigned(1,2)) = to_unsigned(0,2) then`
208			`wr2 <= wr1_i;`
209			`d2_in <= d1_i;`
210			`elsif (mux_sel + to_unsigned(1,2)) = to_unsigned(1,2) then`
211			`wr2 <= wr2_i;`
212			`d2_in <= d2_i;`
213			`elsif (mux_sel + to_unsigned(1,2)) = to_unsigned(2,2) then`
214			`wr2 <= wr3_i;`
215			`d2_in <= d3_i;`
216			`elsif (mux_sel + to_unsigned(1,2)) = to_unsigned(3,2) then`
217			`wr2 <= wr4_i;`
218			`d2_in <= d4_i;`
219			`end if;`
220			`end if;`
221			`end process mux2_process;`
222
223			`--Multiplexer 3(input to RAM 3)`
224			`mux3_process : process(clk_i)`
225			`begin`
226			`if clk_i'event and clk_i = '0' then`
227			`if (mux_sel + to_unsigned(2,2)) = to_unsigned(0,2) then`
228			`wr3 <= wr1_i;`
229			`d3_in <= d1_i;`
230			`elsif (mux_sel + to_unsigned(2,2)) = to_unsigned(1,2) then`
231			`wr3 <= wr2_i;`
232			`d3_in <= d2_i;`
233			`elsif (mux_sel + to_unsigned(2,2)) = to_unsigned(2,2) then`
234			`wr3 <= wr3_i;`
235			`d3_in <= d3_i;`
236			`elsif (mux_sel + to_unsigned(2,2)) = to_unsigned(3,2) then`
237			`wr3 <= wr4_i;`
238			`d3_in <= d4_i;`
239			`end if;`
240			`end if;`
241			`end process mux3_process;`
242
243			`--Multiplexer 4(input to RAM 4)`
244			`mux4_process : process(clk_i)`
245			`begin`
246			`if clk_i'event and clk_i = '0' then`
247			`if (mux_sel + to_unsigned(3,2)) = to_unsigned(0,2) then`
248			`wr4 <= wr1_i;`
249			`d4_in <= d1_i;`
250			`elsif (mux_sel + to_unsigned(3,2)) = to_unsigned(1,2) then`
251			`wr4 <= wr2_i;`
252			`d4_in <= d2_i;`
253			`elsif (mux_sel + to_unsigned(3,2)) = to_unsigned(2,2) then`
254			`wr4 <= wr3_i;`
255			`d4_in <= d3_i;`
256			`elsif (mux_sel + to_unsigned(3,2)) = to_unsigned(3,2) then`
257			`wr4 <= wr4_i;`
258			`d4_in <= d4_i;`
259			`end if;`
260			`end if;`
261			`end process mux4_process;`
262
263			`used_o <= ("00" & unsigned(wr_addr1)) + ("00" & unsigned(wr_addr2)) + ("00" & unsigned(wr_addr3)) + ("00" & unsigned(wr_addr4));`
264
265			`end Behavioral;`