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[/] [c0or1k/] [trunk/] [conts/] [libdev/] [uart/] [pl011/] [uart.h] - Blame information for rev 2

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/*
 * PL011 UART Generic driver implementation.
 * Copyright Bahadir Balban (C) 2009
 */
#ifndef __PL011_H__
#define __PL011_H__
 
#include <l4/config.h> /* To get PLATFORM */
#include <libdev/io.h>
 
#if defined(VARIANT_USERSPACE)
/* FIXME: Take this value in agreement from kernel, or from kernel only */
#include <l4/macros.h>
#include INC_ARCH(io.h)
#define PL011_BASE              USERSPACE_CONSOLE_VBASE
#endif
 
#if defined(VARIANT_BAREMETAL)
#if defined(CONFIG_PLATFORM_PB926)
#define PL011_BASE              0x101F1000
#elif defined(CONFIG_PLATFORM_EB) || defined(CONFIG_PLATFORM_PB11MPCORE)
#define PL011_BASE              0x10009000
#elif defined(CONFIG_PLATFORM_PBA9) || defined(CONFIG_PLATFORM_PBA8)
#define PL011_BASE              0x10009000
#endif
#endif
 
/* Register offsets */
#define PL011_UARTDR            0x00
#define PL011_UARTRSR           0x04
#define PL011_UARTECR           0x04
#define PL011_UARTFR            0x18
#define PL011_UARTILPR          0x20
#define PL011_UARTIBRD          0x24
#define PL011_UARTFBRD          0x28
#define PL011_UARTLCR_H         0x2C
#define PL011_UARTCR            0x30
#define PL011_UARTIFLS          0x34
#define PL011_UARTIMSC          0x38
#define PL011_UARTRIS           0x3C
#define PL011_UARTMIS           0x40
#define PL011_UARTICR           0x44
#define PL011_UARTDMACR         0x48
 
/* IRQ bits for each uart irq event */
#define PL011_RXIRQ             (1 << 4)
#define PL011_TXIRQ             (1 << 5)
#define PL011_RXTIMEOUTIRQ      (1 << 6)
#define PL011_FEIRQ             (1 << 7)
#define PL011_PEIRQ             (1 << 8)
#define PL011_BEIRQ             (1 << 9)
#define PL011_OEIRQ             (1 << 10)
 
 
void pl011_set_baudrate(unsigned long base, unsigned int baud,
                        unsigned int clkrate);
 
#define PL011_UARTEN    (1 << 0)
static inline void pl011_uart_enable(unsigned long base)
{
        unsigned int val = 0;
 
        val = read((base + PL011_UARTCR));
        val |= PL011_UARTEN;
        write(val, (base + PL011_UARTCR));
 
        return;
}
 
static inline void pl011_uart_disable(unsigned long base)
{
        unsigned int val = 0;
 
        val = read((base + PL011_UARTCR));
        val &= ~PL011_UARTEN;
        write(val, (base + PL011_UARTCR));
 
        return;
}
 
#define PL011_TXE       (1 << 8)
static inline void pl011_tx_enable(unsigned long base)
{
        unsigned int val = 0;
 
        val = read((base + PL011_UARTCR));
        val |= PL011_TXE;
        write(val, (base + PL011_UARTCR));
        return;
}
 
static inline void pl011_tx_disable(unsigned long base)
{
        unsigned int val = 0;
 
        val =read((base + PL011_UARTCR));
        val &= ~PL011_TXE;
        write(val, (base + PL011_UARTCR));
        return;
}
 
#define PL011_RXE       (1 << 9)
static inline void pl011_rx_enable(unsigned long base)
{
        unsigned int val = 0;
 
        val = read((base + PL011_UARTCR));
        val |= PL011_RXE;
        write(val, (base + PL011_UARTCR));
        return;
}
 
static inline void pl011_rx_disable(unsigned long base)
{
        unsigned int val = 0;
 
        val = read((base + PL011_UARTCR));
        val &= ~PL011_RXE;
        write(val, (base + PL011_UARTCR));
        return;
}
 
#define PL011_TWO_STOPBITS_SELECT       (1 << 3)
static inline void pl011_set_stopbits(unsigned long base, int stopbits)
{
        unsigned int val = 0;
 
        val = read((base + PL011_UARTLCR_H));
 
        if(stopbits == 2) {                     /* Set to two bits */
                val |= PL011_TWO_STOPBITS_SELECT;
        } else {                                /* Default is 1 */
                val &= ~PL011_TWO_STOPBITS_SELECT;
        }
        write(val, (base + PL011_UARTLCR_H));
        return;
}
 
#define PL011_PARITY_ENABLE     (1 << 1)
static inline void pl011_parity_enable(unsigned long base)
{
        unsigned int val = 0;
 
        val = read((base +PL011_UARTLCR_H));
        val |= PL011_PARITY_ENABLE;
        write(val, (base + PL011_UARTLCR_H));
        return;
}
 
static inline void pl011_parity_disable(unsigned long base)
{
        unsigned int val = 0;
 
        val = read((base + PL011_UARTLCR_H));
        val &= ~PL011_PARITY_ENABLE;
        write(val, (base + PL011_UARTLCR_H));
        return;
}
 
#define PL011_PARITY_EVEN       (1 << 2)
static inline void pl011_set_parity_even(unsigned long base)
{
        unsigned int val = 0;
 
        val = read((base + PL011_UARTLCR_H));
        val |= PL011_PARITY_EVEN;
        write(val, (base + PL011_UARTLCR_H));
        return;
}
 
static inline void pl011_set_parity_odd(unsigned long base)
{
        unsigned int val = 0;
 
        val = read((base + PL011_UARTLCR_H));
        val &= ~PL011_PARITY_EVEN;
        write(val, (base + PL011_UARTLCR_H));
        return;
}
 
#define PL011_ENABLE_FIFOS      (1 << 4)
static inline void pl011_enable_fifos(unsigned long base)
{
        unsigned int val = 0;
 
        val = read((base + PL011_UARTLCR_H));
        val |= PL011_ENABLE_FIFOS;
        write(val, (base + PL011_UARTLCR_H));
        return;
}
 
static inline void pl011_disable_fifos(unsigned long base)
{
        unsigned int val = 0;
 
        val = read((base + PL011_UARTLCR_H));
        val &= ~PL011_ENABLE_FIFOS;
        write(val, (base + PL011_UARTLCR_H));
        return;
}
 
/* Sets the transfer word width for the data register. */
static inline void pl011_set_word_width(unsigned long base, int size)
{
        unsigned int val = 0;
        if(size < 5 || size > 8)        /* Default is 8 */
                size = 8;
 
        /* Clear size field */
        val = read((base + PL011_UARTLCR_H));
        val &= ~(0x3 << 5);
        write(val, (base + PL011_UARTLCR_H));
 
        /*
         * The formula is to write 5 less of size given:
         * 11 = 8 bits
         * 10 = 7 bits
         * 01 = 6 bits
         * 00 = 5 bits
         */
        val = read((base + PL011_UARTLCR_H));
        val |= (size - 5) << 5;
        write(val, (base + PL011_UARTLCR_H));
 
        return;
}
 
/*
 * Defines at which level of fifo fullness an irq will be generated.
 * @xfer: tx fifo = 0, rx fifo = 1
 * @level: Generate irq if:
 * 0    rxfifo >= 1/8 full      txfifo <= 1/8 full
 * 1    rxfifo >= 1/4 full      txfifo <= 1/4 full
 * 2    rxfifo >= 1/2 full      txfifo <= 1/2 full
 * 3    rxfifo >= 3/4 full      txfifo <= 3/4 full
 * 4    rxfifo >= 7/8 full      txfifo <= 7/8 full
 * 5-7  reserved                reserved
 */
static inline void pl011_set_irq_fifolevel(unsigned long base, \
                        unsigned int xfer, unsigned int level)
{
        if(xfer != 1 && xfer != 0)       /* Invalid fifo */
                return;
        if(level > 4)                   /* Invalid level */
                return;
 
        write(level << (xfer * 3), (base + PL011_UARTIFLS));
        return;
}
 
#endif /* __PL011__UART__ */
 

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[/] [c0or1k/] [trunk/] [conts/] [libdev/] [uart/] [pl011/] [uart.h] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	drasko	`/*`
2			`* PL011 UART Generic driver implementation.`
3			`* Copyright Bahadir Balban (C) 2009`
4			`*/`
5			`#ifndef __PL011_H__`
6			`#define __PL011_H__`
7
8			`#include <l4/config.h> /* To get PLATFORM */`
9			`#include <libdev/io.h>`
10
11			`#if defined(VARIANT_USERSPACE)`
12			`/* FIXME: Take this value in agreement from kernel, or from kernel only */`
13			`#include <l4/macros.h>`
14			`#include INC_ARCH(io.h)`
15			`#define PL011_BASE USERSPACE_CONSOLE_VBASE`
16			`#endif`
17
18			`#if defined(VARIANT_BAREMETAL)`
19			`#if defined(CONFIG_PLATFORM_PB926)`
20			`#define PL011_BASE 0x101F1000`
21			`#elif defined(CONFIG_PLATFORM_EB) \|\| defined(CONFIG_PLATFORM_PB11MPCORE)`
22			`#define PL011_BASE 0x10009000`
23			`#elif defined(CONFIG_PLATFORM_PBA9) \|\| defined(CONFIG_PLATFORM_PBA8)`
24			`#define PL011_BASE 0x10009000`
25			`#endif`
26			`#endif`
27
28			`/* Register offsets */`
29			`#define PL011_UARTDR 0x00`
30			`#define PL011_UARTRSR 0x04`
31			`#define PL011_UARTECR 0x04`
32			`#define PL011_UARTFR 0x18`
33			`#define PL011_UARTILPR 0x20`
34			`#define PL011_UARTIBRD 0x24`
35			`#define PL011_UARTFBRD 0x28`
36			`#define PL011_UARTLCR_H 0x2C`
37			`#define PL011_UARTCR 0x30`
38			`#define PL011_UARTIFLS 0x34`
39			`#define PL011_UARTIMSC 0x38`
40			`#define PL011_UARTRIS 0x3C`
41			`#define PL011_UARTMIS 0x40`
42			`#define PL011_UARTICR 0x44`
43			`#define PL011_UARTDMACR 0x48`
44
45			`/* IRQ bits for each uart irq event */`
46			`#define PL011_RXIRQ (1 << 4)`
47			`#define PL011_TXIRQ (1 << 5)`
48			`#define PL011_RXTIMEOUTIRQ (1 << 6)`
49			`#define PL011_FEIRQ (1 << 7)`
50			`#define PL011_PEIRQ (1 << 8)`
51			`#define PL011_BEIRQ (1 << 9)`
52			`#define PL011_OEIRQ (1 << 10)`
53
54
55			`void pl011_set_baudrate(unsigned long base, unsigned int baud,`
56			`unsigned int clkrate);`
57
58			`#define PL011_UARTEN (1 << 0)`
59			`static inline void pl011_uart_enable(unsigned long base)`
60			`{`
61			`unsigned int val = 0;`
62
63			`val = read((base + PL011_UARTCR));`
64			`val \|= PL011_UARTEN;`
65			`write(val, (base + PL011_UARTCR));`
66
67			`return;`
68			`}`
69
70			`static inline void pl011_uart_disable(unsigned long base)`
71			`{`
72			`unsigned int val = 0;`
73
74			`val = read((base + PL011_UARTCR));`
75			`val &= ~PL011_UARTEN;`
76			`write(val, (base + PL011_UARTCR));`
77
78			`return;`
79			`}`
80
81			`#define PL011_TXE (1 << 8)`
82			`static inline void pl011_tx_enable(unsigned long base)`
83			`{`
84			`unsigned int val = 0;`
85
86			`val = read((base + PL011_UARTCR));`
87			`val \|= PL011_TXE;`
88			`write(val, (base + PL011_UARTCR));`
89			`return;`
90			`}`
91
92			`static inline void pl011_tx_disable(unsigned long base)`
93			`{`
94			`unsigned int val = 0;`
95
96			`val =read((base + PL011_UARTCR));`
97			`val &= ~PL011_TXE;`
98			`write(val, (base + PL011_UARTCR));`
99			`return;`
100			`}`
101
102			`#define PL011_RXE (1 << 9)`
103			`static inline void pl011_rx_enable(unsigned long base)`
104			`{`
105			`unsigned int val = 0;`
106
107			`val = read((base + PL011_UARTCR));`
108			`val \|= PL011_RXE;`
109			`write(val, (base + PL011_UARTCR));`
110			`return;`
111			`}`
112
113			`static inline void pl011_rx_disable(unsigned long base)`
114			`{`
115			`unsigned int val = 0;`
116
117			`val = read((base + PL011_UARTCR));`
118			`val &= ~PL011_RXE;`
119			`write(val, (base + PL011_UARTCR));`
120			`return;`
121			`}`
122
123			`#define PL011_TWO_STOPBITS_SELECT (1 << 3)`
124			`static inline void pl011_set_stopbits(unsigned long base, int stopbits)`
125			`{`
126			`unsigned int val = 0;`
127
128			`val = read((base + PL011_UARTLCR_H));`
129
130			`if(stopbits == 2) { /* Set to two bits */`
131			`val \|= PL011_TWO_STOPBITS_SELECT;`
132			`} else { /* Default is 1 */`
133			`val &= ~PL011_TWO_STOPBITS_SELECT;`
134			`}`
135			`write(val, (base + PL011_UARTLCR_H));`
136			`return;`
137			`}`
138
139			`#define PL011_PARITY_ENABLE (1 << 1)`
140			`static inline void pl011_parity_enable(unsigned long base)`
141			`{`
142			`unsigned int val = 0;`
143
144			`val = read((base +PL011_UARTLCR_H));`
145			`val \|= PL011_PARITY_ENABLE;`
146			`write(val, (base + PL011_UARTLCR_H));`
147			`return;`
148			`}`
149
150			`static inline void pl011_parity_disable(unsigned long base)`
151			`{`
152			`unsigned int val = 0;`
153
154			`val = read((base + PL011_UARTLCR_H));`
155			`val &= ~PL011_PARITY_ENABLE;`
156			`write(val, (base + PL011_UARTLCR_H));`
157			`return;`
158			`}`
159
160			`#define PL011_PARITY_EVEN (1 << 2)`
161			`static inline void pl011_set_parity_even(unsigned long base)`
162			`{`
163			`unsigned int val = 0;`
164
165			`val = read((base + PL011_UARTLCR_H));`
166			`val \|= PL011_PARITY_EVEN;`
167			`write(val, (base + PL011_UARTLCR_H));`
168			`return;`
169			`}`
170
171			`static inline void pl011_set_parity_odd(unsigned long base)`
172			`{`
173			`unsigned int val = 0;`
174
175			`val = read((base + PL011_UARTLCR_H));`
176			`val &= ~PL011_PARITY_EVEN;`
177			`write(val, (base + PL011_UARTLCR_H));`
178			`return;`
179			`}`
180
181			`#define PL011_ENABLE_FIFOS (1 << 4)`
182			`static inline void pl011_enable_fifos(unsigned long base)`
183			`{`
184			`unsigned int val = 0;`
185
186			`val = read((base + PL011_UARTLCR_H));`
187			`val \|= PL011_ENABLE_FIFOS;`
188			`write(val, (base + PL011_UARTLCR_H));`
189			`return;`
190			`}`
191
192			`static inline void pl011_disable_fifos(unsigned long base)`
193			`{`
194			`unsigned int val = 0;`
195
196			`val = read((base + PL011_UARTLCR_H));`
197			`val &= ~PL011_ENABLE_FIFOS;`
198			`write(val, (base + PL011_UARTLCR_H));`
199			`return;`
200			`}`
201
202			`/* Sets the transfer word width for the data register. */`
203			`static inline void pl011_set_word_width(unsigned long base, int size)`
204			`{`
205			`unsigned int val = 0;`
206			`if(size < 5 \|\| size > 8) /* Default is 8 */`
207			`size = 8;`
208
209			`/* Clear size field */`
210			`val = read((base + PL011_UARTLCR_H));`
211			`val &= ~(0x3 << 5);`
212			`write(val, (base + PL011_UARTLCR_H));`
213
214			`/*`
215			`* The formula is to write 5 less of size given:`
216			`* 11 = 8 bits`
217			`* 10 = 7 bits`
218			`* 01 = 6 bits`
219			`* 00 = 5 bits`
220			`*/`
221			`val = read((base + PL011_UARTLCR_H));`
222			`val \|= (size - 5) << 5;`
223			`write(val, (base + PL011_UARTLCR_H));`
224
225			`return;`
226			`}`
227
228			`/*`
229			`* Defines at which level of fifo fullness an irq will be generated.`
230			`* @xfer: tx fifo = 0, rx fifo = 1`
231			`* @level: Generate irq if:`
232			`* 0 rxfifo >= 1/8 full txfifo <= 1/8 full`
233			`* 1 rxfifo >= 1/4 full txfifo <= 1/4 full`
234			`* 2 rxfifo >= 1/2 full txfifo <= 1/2 full`
235			`* 3 rxfifo >= 3/4 full txfifo <= 3/4 full`
236			`* 4 rxfifo >= 7/8 full txfifo <= 7/8 full`
237			`* 5-7 reserved reserved`
238			`*/`
239			`static inline void pl011_set_irq_fifolevel(unsigned long base, \`
240			`unsigned int xfer, unsigned int level)`
241			`{`
242			`if(xfer != 1 && xfer != 0) /* Invalid fifo */`
243			`return;`
244			`if(level > 4) /* Invalid level */`
245			`return;`
246
247			`write(level << (xfer * 3), (base + PL011_UARTIFLS));`
248			`return;`
249			`}`
250
251			`#endif /* __PL011__UART__ */`
252