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/*
 * ARMv7 Performance Monitor operations
 *
 * Copyright (C) 2010 B Labs Ltd.
 *
 * Author: Bahadir Balban
 */
#ifndef __PERFMON_H__
#define __PERFMON_H__
 
#include <l4lib/types.h>
 
/* Perfmon control register */
#define PMCR_DP_BIT                     5 /* Disable prohibited */
#define PMCR_X_BIT                      4 /* Export event enable */
#define PMCR_D_BIT                      3 /* 64-cycle granularity */
#define PMCR_C_BIT                      2 /* PMCCNTR reset */
#define PMCR_P_BIT                      1 /* Events all reset */
#define PMCR_E_BIT                      0 /* Enable all */
 
/* Obtain number of event counters */
#define PMCR_N_SHIFT                    11
#define PMCR_N_MASK                     0x1F
 
/* Special bit for cycle counter */
#define PMCCNTR_BIT                     31
 
 
/*
 * Performance Events
 */
 
/* Generic v7 events */
#define PERFMON_EVENT_SOFTINC                   0
#define PERFMON_EVENT_IFETCH_L1CREFILL          1
#define PERFMON_EVENT_IFETCH_TLBREFILL          2
#define PERFMON_EVENT_DFETCH_L1CREFILL          3
#define PERFMON_EVENT_DFETCH_L1CACCESS          4
#define PERFMON_EVENT_DFETCH_TLBREFILL          5
#define PERFMON_EVENT_MEMREAD_INSTR             6
#define PERFMON_EVENT_MEMWRITE_INSTR            7
#define PERFMON_EVENT_ALL_INSTR                 8
#define PERFMON_EVENT_EXCEPTION                 9
#define PERFMON_EVENT_EXCEPTION_RETURN          10
#define PERFMON_EVENT_CONTEXTIDR_CHANGE         11
#define PERFMON_EVENT_PC_CHANGE                 12
#define PERFMON_EVENT_IMM_BRANCH                13
#define PERFMON_EVENT_FUNCTION_RETURN           14
#define PERFMON_EVENT_UNALIGNED_ACCESS          15
#define PERFMON_EVENT_BRANCH_MISS               16
#define PERFMON_EVENT_RAW_CYCLE_COUNT           17
#define PERFMON_EVENT_BRANCH_MAYBEHIT           18
 
/*
 * Cortex-A9 events (only relevant ones)
 * 0x40-2, 0x6E, 0x70, 0x71-4, 0x80-0x81, 0x8A-8B
 * 0xA0-5 omitted
 */
 
/*
 * Linefill not satisfied from other cpu caches but
 * has to go to external memory
 */
#define PERFMON_EVENT_SMP_LINEFILL_MISS         0x50
 
/* Linefill satisfied from other cpu caches */
#define PERFMON_EVENT_SMP_LINEFILL_HIT          0x51
 
/* Icache refill stall cycles on cpu pipeline */
#define PERFMON_EVENT_ICACHE_CPU_STALL          0x60
 
/* Dcache refill stall cycles on cpu pipeline */
#define PERFMON_EVENT_DCACHE_CPU_STALL          0x61
 
/* TLB miss stall cycles on cpu pipeline */
#define PERFMON_EVENT_TLBMISS_CPU_STALL         0x62
 
#define PERFMON_EVENT_STREX_SUCCESS             0x63
#define PERFMON_EVENT_STREX_FAIL                0x64
#define PERFMON_EVENT_DCACHE_EVICTION           0x65
 
/* Issue stage can't proceed to dispatch any instruction */
#define PERFMON_EVENT_PIPELINE_CANT_ISSUE       0x66
 
/* Issue stage empty */
#define PERFMON_EVENT_PIPELINE_ISSUE_EMPTY      0x67
 
/* Register renamed instructions */
#define PERFMON_EVENT_REGRENAMED_INSTR          0x68
 
#define PERFMON_EVENT_CPUSTALL_ITLB_MISS        0x82
#define PERFMON_EVENT_CPUSTALL_DTLB_MISS        0x83
#define PERFMON_EVENT_CPUSTALL_IUTLB_MISS       0x84
#define PERFMON_EVENT_CPUSTALL_DUTLB_MISS       0x85
#define PERFMON_EVENT_CPUSTALL_DMB              0x86
#define PERFMON_EVENT_ISB_COUNT                 0x90
#define PERFMON_EVENT_DSB_COUNT                 0x91
#define PERFMON_EVENT_DMB_COUNT                 0x92
#define PERFMON_EVENT_EXTIRQ_COUNT              0x93
 
 
static inline u32 __attribute__((always_inline))
cp15_read_perfmon_ctrl(void)
{
        volatile u32 val = 0;
 
        __asm__ __volatile__ (
                "mrc p15, 0, %0, c9, c12, 0\n"
                "isb\n"
                : "=r" (val)
                :
        );
 
        return val;
}
 
static inline void __attribute__((always_inline))
cp15_write_perfmon_ctrl(volatile u32 word)
{
        __asm__ __volatile__ (
                "mcr p15, 0, %0, c9, c12, 0"
                :
                : "r" (word)
        );
}
 
static inline u32 __attribute__((always_inline))
cp15_read_perfmon_cntenset(void)
{
        volatile u32 val = 0;
 
        __asm__ __volatile__ (
                "mrc p15, 0, %0, c9, c12, 1\n"
                "isb\n"
                : "=r" (val)
                :
        );
 
        return val;
}
 
static inline void __attribute__((always_inline))
cp15_write_perfmon_cntenset(volatile u32 word)
{
        __asm__ __volatile__ (
                "mcr p15, 0, %0, c9, c12, 1"
                :
                : "r" (word)
        );
}
 
static inline u32 __attribute__((always_inline))
cp15_read_perfmon_cntenclr(void)
{
        u32 val = 0;
 
        __asm__ __volatile__ (
                "mrc p15, 0, %0, c9, c12, 2"
                : "=r" (val)
                :
        );
 
        return val;
}
 
static inline void __attribute__((always_inline))
cp15_write_perfmon_cntenclr(volatile u32 word)
{
        __asm__ __volatile__ (
                "mcr p15, 0, %0, c9, c12, 2"
                :
                : "r" (word)
        );
}
 
 
static inline u32 __attribute__((always_inline))
cp15_read_perfmon_overflow(void)
{
        u32 val = 0;
 
        __asm__ __volatile__ (
                "mrc p15, 0, %0, c9, c12, 3"
                : "=r" (val)
                :
        );
 
        return val;
}
 
static inline void __attribute__((always_inline))
cp15_write_perfmon_overflow(volatile u32 word)
{
        __asm__ __volatile__ (
                "mcr p15, 0, %0, c9, c12, 3"
                :
                : "r" (word)
        );
}
 
static inline void __attribute__((always_inline))
cp15_write_perfmon_softinc(volatile u32 word)
{
        __asm__ __volatile__ (
                "mcr p15, 0, %0, c9, c12, 4"
                :
                : "r" (word)
        );
}
 
static inline u32 __attribute__((always_inline))
cp15_read_perfmon_evcntsel(void)
{
        u32 val = 0;
 
        __asm__ __volatile__ (
                "mrc p15, 0, %0, c9, c12, 5"
                : "=r" (val)
                :
        );
 
        return val;
}
 
static inline void __attribute__((always_inline))
cp15_write_perfmon_evcntsel(volatile u32 word)
{
        __asm__ __volatile__ (
                "mcr p15, 0, %0, c9, c12, 5"
                :
                : "r" (word)
        );
}
 
static inline u32 __attribute__((always_inline))
cp15_read_perfmon_cyccnt(void)
{
        volatile u32 val = 0;
 
        __asm__ __volatile__ (
                "mrc p15, 0, %0, c9, c13, 0\n"
                "isb\n"
                : "=r" (val)
                :
        );
 
        return val;
}
 
static inline void __attribute__((always_inline))
cp15_write_perfmon_cyccnt(volatile u32 word)
{
        __asm__ __volatile__ (
                "mcr p15, 0, %0, c9, c13, 0"
                :
                : "r" (word)
        );
}
 
static inline u32 __attribute__((always_inline))
cp15_read_perfmon_evtypesel(void)
{
        u32 val = 0;
 
        __asm__ __volatile__ (
                "mrc p15, 0, %0, c9, c13, 1"
                : "=r" (val)
                :
        );
 
        return val;
}
 
static inline void __attribute__((always_inline))
cp15_write_perfmon_evtypesel(volatile u32 word)
{
        __asm__ __volatile__ (
                "mcr p15, 0, %0, c9, c13, 1"
                :
                : "r" (word)
        );
}
 
static inline u32 __attribute__((always_inline))
cp15_read_perfmon_evcnt(void)
{
        u32 val = 0;
 
        __asm__ __volatile__ (
                "mrc p15, 0, %0, c9, c13, 2"
                : "=r" (val)
                :
        );
 
        return val;
}
 
static inline void __attribute__((always_inline))
cp15_write_perfmon_evcnt(volatile u32 word)
{
        __asm__ __volatile__ (
                "mcr p15, 0, %0, c9, c13, 2"
                :
                : "r" (word)
        );
}
 
 
static inline u32 __attribute__((always_inline))
cp15_read_perfmon_useren(void)
{
        u32 val = 0;
 
        __asm__ __volatile__ (
                "mrc p15, 0, %0, c9, c14, 0"
                : "=r" (val)
                :
        );
 
        return val;
}
 
static inline void __attribute__((always_inline))
cp15_write_perfmon_useren(volatile u32 word)
{
        __asm__ __volatile__ (
                "mcr p15, 0, %0, c9, c14, 0"
                :
                : "r" (word)
        );
}
 
static inline u32 __attribute__((always_inline))
cp15_read_perfmon_intenset(void)
{
        u32 val = 0;
 
        __asm__ __volatile__ (
                "mrc p15, 0, %0, c9, c14, 1"
                : "=r" (val)
                :
        );
 
        return val;
}
 
static inline void __attribute__((always_inline))
cp15_write_perfmon_intenset(volatile u32 word)
{
        __asm__ __volatile__ (
                "mcr p15, 0, %0, c9, c14, 1"
                :
                : "r" (word)
        );
}
 
static inline u32 __attribute__((always_inline))
cp15_read_perfmon_intenclr(void)
{
        u32 val = 0;
 
        __asm__ __volatile__ (
                "mrc p15, 0, %0, c9, c14, 2"
                : "=r" (val)
                :
        );
 
        return val;
}
 
static inline void __attribute__((always_inline))
cp15_write_perfmon_intenclr(volatile u32 word)
{
        __asm__ __volatile__ (
                "mcr p15, 0, %0, c9, c14, 2"
                :
                : "r" (word)
        );
}
 
#include <stdio.h>
 
#if defined (CONFIG_DEBUG_PERFMON_USER)
static inline
u32 perfmon_read_cyccnt()
{
        u32 cnt = cp15_read_perfmon_cyccnt();
        u32 ovfl = cp15_read_perfmon_overflow();
 
        /* Detect overflow and signal something was wrong */
        if (ovfl & (1 << PMCCNTR_BIT))
                printf("%s: Overflow.\n", __FUNCTION__);
        return cnt;
}
 
void perfmon_reset_start_cyccnt();
u32 perfmon_read_reset_start_cyccnt();
 
#endif
 
 
void perfmon_init();
 
#endif /* __PERFMON_H__ */
 

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[/] [c0or1k/] [trunk/] [conts/] [libl4/] [include/] [l4lib/] [arch/] [arm/] [v7/] [perfmon.h] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	drasko	`/*`
2			`* ARMv7 Performance Monitor operations`
3			`*`
4			`* Copyright (C) 2010 B Labs Ltd.`
5			`*`
6			`* Author: Bahadir Balban`
7			`*/`
8			`#ifndef __PERFMON_H__`
9			`#define __PERFMON_H__`
10
11			`#include <l4lib/types.h>`
12
13			`/* Perfmon control register */`
14			`#define PMCR_DP_BIT 5 /* Disable prohibited */`
15			`#define PMCR_X_BIT 4 /* Export event enable */`
16			`#define PMCR_D_BIT 3 /* 64-cycle granularity */`
17			`#define PMCR_C_BIT 2 /* PMCCNTR reset */`
18			`#define PMCR_P_BIT 1 /* Events all reset */`
19			`#define PMCR_E_BIT 0 /* Enable all */`
20
21			`/* Obtain number of event counters */`
22			`#define PMCR_N_SHIFT 11`
23			`#define PMCR_N_MASK 0x1F`
24
25			`/* Special bit for cycle counter */`
26			`#define PMCCNTR_BIT 31`
27
28
29			`/*`
30			`* Performance Events`
31			`*/`
32
33			`/* Generic v7 events */`
34			`#define PERFMON_EVENT_SOFTINC 0`
35			`#define PERFMON_EVENT_IFETCH_L1CREFILL 1`
36			`#define PERFMON_EVENT_IFETCH_TLBREFILL 2`
37			`#define PERFMON_EVENT_DFETCH_L1CREFILL 3`
38			`#define PERFMON_EVENT_DFETCH_L1CACCESS 4`
39			`#define PERFMON_EVENT_DFETCH_TLBREFILL 5`
40			`#define PERFMON_EVENT_MEMREAD_INSTR 6`
41			`#define PERFMON_EVENT_MEMWRITE_INSTR 7`
42			`#define PERFMON_EVENT_ALL_INSTR 8`
43			`#define PERFMON_EVENT_EXCEPTION 9`
44			`#define PERFMON_EVENT_EXCEPTION_RETURN 10`
45			`#define PERFMON_EVENT_CONTEXTIDR_CHANGE 11`
46			`#define PERFMON_EVENT_PC_CHANGE 12`
47			`#define PERFMON_EVENT_IMM_BRANCH 13`
48			`#define PERFMON_EVENT_FUNCTION_RETURN 14`
49			`#define PERFMON_EVENT_UNALIGNED_ACCESS 15`
50			`#define PERFMON_EVENT_BRANCH_MISS 16`
51			`#define PERFMON_EVENT_RAW_CYCLE_COUNT 17`
52			`#define PERFMON_EVENT_BRANCH_MAYBEHIT 18`
53
54			`/*`
55			`* Cortex-A9 events (only relevant ones)`
56			`* 0x40-2, 0x6E, 0x70, 0x71-4, 0x80-0x81, 0x8A-8B`
57			`* 0xA0-5 omitted`
58			`*/`
59
60			`/*`
61			`* Linefill not satisfied from other cpu caches but`
62			`* has to go to external memory`
63			`*/`
64			`#define PERFMON_EVENT_SMP_LINEFILL_MISS 0x50`
65
66			`/* Linefill satisfied from other cpu caches */`
67			`#define PERFMON_EVENT_SMP_LINEFILL_HIT 0x51`
68
69			`/* Icache refill stall cycles on cpu pipeline */`
70			`#define PERFMON_EVENT_ICACHE_CPU_STALL 0x60`
71
72			`/* Dcache refill stall cycles on cpu pipeline */`
73			`#define PERFMON_EVENT_DCACHE_CPU_STALL 0x61`
74
75			`/* TLB miss stall cycles on cpu pipeline */`
76			`#define PERFMON_EVENT_TLBMISS_CPU_STALL 0x62`
77
78			`#define PERFMON_EVENT_STREX_SUCCESS 0x63`
79			`#define PERFMON_EVENT_STREX_FAIL 0x64`
80			`#define PERFMON_EVENT_DCACHE_EVICTION 0x65`
81
82			`/* Issue stage can't proceed to dispatch any instruction */`
83			`#define PERFMON_EVENT_PIPELINE_CANT_ISSUE 0x66`
84
85			`/* Issue stage empty */`
86			`#define PERFMON_EVENT_PIPELINE_ISSUE_EMPTY 0x67`
87
88			`/* Register renamed instructions */`
89			`#define PERFMON_EVENT_REGRENAMED_INSTR 0x68`
90
91			`#define PERFMON_EVENT_CPUSTALL_ITLB_MISS 0x82`
92			`#define PERFMON_EVENT_CPUSTALL_DTLB_MISS 0x83`
93			`#define PERFMON_EVENT_CPUSTALL_IUTLB_MISS 0x84`
94			`#define PERFMON_EVENT_CPUSTALL_DUTLB_MISS 0x85`
95			`#define PERFMON_EVENT_CPUSTALL_DMB 0x86`
96			`#define PERFMON_EVENT_ISB_COUNT 0x90`
97			`#define PERFMON_EVENT_DSB_COUNT 0x91`
98			`#define PERFMON_EVENT_DMB_COUNT 0x92`
99			`#define PERFMON_EVENT_EXTIRQ_COUNT 0x93`
100
101
102			`static inline u32 __attribute__((always_inline))`
103			`cp15_read_perfmon_ctrl(void)`
104			`{`
105			`volatile u32 val = 0;`
106
107			`__asm__ __volatile__ (`
108			`"mrc p15, 0, %0, c9, c12, 0\n"`
109			`"isb\n"`
110			`: "=r" (val)`
111			`:`
112			`);`
113
114			`return val;`
115			`}`
116
117			`static inline void __attribute__((always_inline))`
118			`cp15_write_perfmon_ctrl(volatile u32 word)`
119			`{`
120			`__asm__ __volatile__ (`
121			`"mcr p15, 0, %0, c9, c12, 0"`
122			`:`
123			`: "r" (word)`
124			`);`
125			`}`
126
127			`static inline u32 __attribute__((always_inline))`
128			`cp15_read_perfmon_cntenset(void)`
129			`{`
130			`volatile u32 val = 0;`
131
132			`__asm__ __volatile__ (`
133			`"mrc p15, 0, %0, c9, c12, 1\n"`
134			`"isb\n"`
135			`: "=r" (val)`
136			`:`
137			`);`
138
139			`return val;`
140			`}`
141
142			`static inline void __attribute__((always_inline))`
143			`cp15_write_perfmon_cntenset(volatile u32 word)`
144			`{`
145			`__asm__ __volatile__ (`
146			`"mcr p15, 0, %0, c9, c12, 1"`
147			`:`
148			`: "r" (word)`
149			`);`
150			`}`
151
152			`static inline u32 __attribute__((always_inline))`
153			`cp15_read_perfmon_cntenclr(void)`
154			`{`
155			`u32 val = 0;`
156
157			`__asm__ __volatile__ (`
158			`"mrc p15, 0, %0, c9, c12, 2"`
159			`: "=r" (val)`
160			`:`
161			`);`
162
163			`return val;`
164			`}`
165
166			`static inline void __attribute__((always_inline))`
167			`cp15_write_perfmon_cntenclr(volatile u32 word)`
168			`{`
169			`__asm__ __volatile__ (`
170			`"mcr p15, 0, %0, c9, c12, 2"`
171			`:`
172			`: "r" (word)`
173			`);`
174			`}`
175
176
177			`static inline u32 __attribute__((always_inline))`
178			`cp15_read_perfmon_overflow(void)`
179			`{`
180			`u32 val = 0;`
181
182			`__asm__ __volatile__ (`
183			`"mrc p15, 0, %0, c9, c12, 3"`
184			`: "=r" (val)`
185			`:`
186			`);`
187
188			`return val;`
189			`}`
190
191			`static inline void __attribute__((always_inline))`
192			`cp15_write_perfmon_overflow(volatile u32 word)`
193			`{`
194			`__asm__ __volatile__ (`
195			`"mcr p15, 0, %0, c9, c12, 3"`
196			`:`
197			`: "r" (word)`
198			`);`
199			`}`
200
201			`static inline void __attribute__((always_inline))`
202			`cp15_write_perfmon_softinc(volatile u32 word)`
203			`{`
204			`__asm__ __volatile__ (`
205			`"mcr p15, 0, %0, c9, c12, 4"`
206			`:`
207			`: "r" (word)`
208			`);`
209			`}`
210
211			`static inline u32 __attribute__((always_inline))`
212			`cp15_read_perfmon_evcntsel(void)`
213			`{`
214			`u32 val = 0;`
215
216			`__asm__ __volatile__ (`
217			`"mrc p15, 0, %0, c9, c12, 5"`
218			`: "=r" (val)`
219			`:`
220			`);`
221
222			`return val;`
223			`}`
224
225			`static inline void __attribute__((always_inline))`
226			`cp15_write_perfmon_evcntsel(volatile u32 word)`
227			`{`
228			`__asm__ __volatile__ (`
229			`"mcr p15, 0, %0, c9, c12, 5"`
230			`:`
231			`: "r" (word)`
232			`);`
233			`}`
234
235			`static inline u32 __attribute__((always_inline))`
236			`cp15_read_perfmon_cyccnt(void)`
237			`{`
238			`volatile u32 val = 0;`
239
240			`__asm__ __volatile__ (`
241			`"mrc p15, 0, %0, c9, c13, 0\n"`
242			`"isb\n"`
243			`: "=r" (val)`
244			`:`
245			`);`
246
247			`return val;`
248			`}`
249
250			`static inline void __attribute__((always_inline))`
251			`cp15_write_perfmon_cyccnt(volatile u32 word)`
252			`{`
253			`__asm__ __volatile__ (`
254			`"mcr p15, 0, %0, c9, c13, 0"`
255			`:`
256			`: "r" (word)`
257			`);`
258			`}`
259
260			`static inline u32 __attribute__((always_inline))`
261			`cp15_read_perfmon_evtypesel(void)`
262			`{`
263			`u32 val = 0;`
264
265			`__asm__ __volatile__ (`
266			`"mrc p15, 0, %0, c9, c13, 1"`
267			`: "=r" (val)`
268			`:`
269			`);`
270
271			`return val;`
272			`}`
273
274			`static inline void __attribute__((always_inline))`
275			`cp15_write_perfmon_evtypesel(volatile u32 word)`
276			`{`
277			`__asm__ __volatile__ (`
278			`"mcr p15, 0, %0, c9, c13, 1"`
279			`:`
280			`: "r" (word)`
281			`);`
282			`}`
283
284			`static inline u32 __attribute__((always_inline))`
285			`cp15_read_perfmon_evcnt(void)`
286			`{`
287			`u32 val = 0;`
288
289			`__asm__ __volatile__ (`
290			`"mrc p15, 0, %0, c9, c13, 2"`
291			`: "=r" (val)`
292			`:`
293			`);`
294
295			`return val;`
296			`}`
297
298			`static inline void __attribute__((always_inline))`
299			`cp15_write_perfmon_evcnt(volatile u32 word)`
300			`{`
301			`__asm__ __volatile__ (`
302			`"mcr p15, 0, %0, c9, c13, 2"`
303			`:`
304			`: "r" (word)`
305			`);`
306			`}`
307
308
309			`static inline u32 __attribute__((always_inline))`
310			`cp15_read_perfmon_useren(void)`
311			`{`
312			`u32 val = 0;`
313
314			`__asm__ __volatile__ (`
315			`"mrc p15, 0, %0, c9, c14, 0"`
316			`: "=r" (val)`
317			`:`
318			`);`
319
320			`return val;`
321			`}`
322
323			`static inline void __attribute__((always_inline))`
324			`cp15_write_perfmon_useren(volatile u32 word)`
325			`{`
326			`__asm__ __volatile__ (`
327			`"mcr p15, 0, %0, c9, c14, 0"`
328			`:`
329			`: "r" (word)`
330			`);`
331			`}`
332
333			`static inline u32 __attribute__((always_inline))`
334			`cp15_read_perfmon_intenset(void)`
335			`{`
336			`u32 val = 0;`
337
338			`__asm__ __volatile__ (`
339			`"mrc p15, 0, %0, c9, c14, 1"`
340			`: "=r" (val)`
341			`:`
342			`);`
343
344			`return val;`
345			`}`
346
347			`static inline void __attribute__((always_inline))`
348			`cp15_write_perfmon_intenset(volatile u32 word)`
349			`{`
350			`__asm__ __volatile__ (`
351			`"mcr p15, 0, %0, c9, c14, 1"`
352			`:`
353			`: "r" (word)`
354			`);`
355			`}`
356
357			`static inline u32 __attribute__((always_inline))`
358			`cp15_read_perfmon_intenclr(void)`
359			`{`
360			`u32 val = 0;`
361
362			`__asm__ __volatile__ (`
363			`"mrc p15, 0, %0, c9, c14, 2"`
364			`: "=r" (val)`
365			`:`
366			`);`
367
368			`return val;`
369			`}`
370
371			`static inline void __attribute__((always_inline))`
372			`cp15_write_perfmon_intenclr(volatile u32 word)`
373			`{`
374			`__asm__ __volatile__ (`
375			`"mcr p15, 0, %0, c9, c14, 2"`
376			`:`
377			`: "r" (word)`
378			`);`
379			`}`
380
381			`#include <stdio.h>`
382
383			`#if defined (CONFIG_DEBUG_PERFMON_USER)`
384			`static inline`
385			`u32 perfmon_read_cyccnt()`
386			`{`
387			`u32 cnt = cp15_read_perfmon_cyccnt();`
388			`u32 ovfl = cp15_read_perfmon_overflow();`
389
390			`/* Detect overflow and signal something was wrong */`
391			`if (ovfl & (1 << PMCCNTR_BIT))`
392			`printf("%s: Overflow.\n", __FUNCTION__);`
393			`return cnt;`
394			`}`
395
396			`void perfmon_reset_start_cyccnt();`
397			`u32 perfmon_read_reset_start_cyccnt();`
398
399			`#endif`
400
401
402			`void perfmon_init();`
403
404			`#endif /* __PERFMON_H__ */`
405