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[/] [c0or1k/] [trunk/] [conts/] [libl4/] [src/] [arch/] [arm/] [v7/] [perfmon.c] - Blame information for rev 2

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1 2 drasko
/*
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 * Performance monitoring
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 *
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 * Copyright (C) 2010 B Labs Ltd.
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 *
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 * Author: Bahadir Balban
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 */
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#include <l4lib/perfmon.h>
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#if defined (CONFIG_DEBUG_PERFMON_USER)
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/*
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 * Resets/restarts cycle counter
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 */
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void perfmon_reset_start_cyccnt()
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{
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        volatile u32 pmcctrl;
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        /* Disable the cycle counter register */
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        cp15_write_perfmon_cntenclr(1 << PMCCNTR_BIT);
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        /* Clear the cycle counter on ctrl register */
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        pmcctrl = cp15_read_perfmon_ctrl();
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        pmcctrl |= (1 << PMCR_C_BIT);
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        cp15_write_perfmon_ctrl(pmcctrl);
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        /* Clear overflow register */
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        cp15_write_perfmon_overflow(1 << PMCCNTR_BIT);
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        /* Enable the cycle count */
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        cp15_write_perfmon_cntenset(1 << PMCCNTR_BIT);
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}
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/*
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 * Reads current counter, clears and restarts it
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 */
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u32 perfmon_read_reset_start_cyccnt()
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{
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        volatile u32 cyccnt = cp15_read_perfmon_cyccnt();
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        perfmon_reset_start_cyccnt();
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        return cyccnt;
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}
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#endif /* End of !CONFIG_DEBUG_PERFMON_USER */

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