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[/] [c0or1k/] [trunk/] [include/] [l4/] [drivers/] [irq/] [pl190/] [pl190_vic.h] - Blame information for rev 2

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1 2 drasko
/*
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 * PL190 Primecell Vectored Interrupt Controller offsets
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 *
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 * Copyright (C) 2007 Bahadir Balban
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 *
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 */
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#ifndef __PL190_VIC_H__
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#define __PL190_VIC_H__
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#include INC_PLAT(platform.h)
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#include INC_ARCH(types.h)
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#include INC_ARCH(io.h)
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#define PL190_BASE                              PLATFORM_IRQCTRL0_VBASE
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#define PL190_SIC_BASE                          PLATFORM_IRQCTRL1_VBASE
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#define PL190_IRQS_MAX                          32
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/* VIC register offsets */
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#define PL190_VIC_IRQSTATUS                     (PL190_BASE + 0x00)
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#define PL190_VIC_FIQSTATUS                     (PL190_BASE + 0x04)
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#define PL190_VIC_RAWINTR                       (PL190_BASE + 0x08)
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#define PL190_VIC_INTSELECT                     (PL190_BASE + 0x0C)
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#define PL190_VIC_INTENABLE                     (PL190_BASE + 0x10)
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#define PL190_VIC_INTENCLEAR                    (PL190_BASE + 0x14)
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#define PL190_VIC_SOFTINT                       (PL190_BASE + 0x18)
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#define PL190_VIC_SOFTINTCLEAR                  (PL190_BASE + 0x1C)
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#define PL190_VIC_PROTECTION                    (PL190_BASE + 0x20)
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#define PL190_VIC_VECTADDR                      (PL190_BASE + 0x30)
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#define PL190_VIC_DEFVECTADDR                   (PL190_BASE + 0x34)
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#define PL190_VIC_VECTADDR0                     (PL190_BASE + 0x100)
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/* 15 PIC_VECTADDR registers up to      0x13C */
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#define PL190_VIC_VECTCNTL0                     (PL190_BASE + 0x200)
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/* 15 PIC_VECTCNTL registers up to      0x23C */
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#define PL190_SIC_IRQS_MAX                      32
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#define PL190_SIC_STATUS                        (PL190_SIC_BASE + 0x0)
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#define PL190_SIC_RAWSTAT                       (PL190_SIC_BASE + 0x04)
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#define PL190_SIC_ENABLE                        (PL190_SIC_BASE + 0x08)
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#define PL190_SIC_ENSET                         (PL190_SIC_BASE + 0x08)
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#define PL190_SIC_ENCLR                         (PL190_SIC_BASE + 0x0C)
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#define PL190_SIC_SOFTINTSET                    (PL190_SIC_BASE + 0x10)
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#define PL190_SIC_SOFTINTCLR                    (PL190_SIC_BASE + 0x14)
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#define PL190_SIC_PICENABLE                     (PL190_SIC_BASE + 0x20)
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#define PL190_SIC_PICENSET                      (PL190_SIC_BASE + 0x20)
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#define PL190_SIC_PICENCLR                      (PL190_SIC_BASE + 0x24)
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void pl190_vic_init(void);
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void pl190_ack_irq(l4id_t irq);
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void pl190_mask_irq(l4id_t irq);
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void pl190_unmask_irq(l4id_t irq);
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l4id_t pl190_read_irq(void *irq_chip_data);
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l4id_t pl190_sic_read_irq(void *irq_chip_data);
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void pl190_sic_mask_irq(l4id_t irq);
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void pl190_sic_mask_irq(l4id_t irq);
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void pl190_sic_ack_irq(l4id_t irq);
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void pl190_sic_unmask_irq(l4id_t irq);
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void pl190_sic_init(void);
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#endif /* __PL190_VIC_H__ */

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