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[/] [c0or1k/] [trunk/] [include/] [l4/] [platform/] [eb/] [sysctrl.h] - Blame information for rev 2

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Line No. Rev Author Line
1 2 drasko
#ifndef __EB_SYSCTRL_H__
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#define __EB_SYSCTRL_H__
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/* TODO: Better to stick this file in a ARM specific folder as most realview boards
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 * tend to have this component
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 */
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#define SYS_ID                  0x0000
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#define SYS_SW                  0x0004
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#define SYS_LED                 0x0008
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#define SYS_OSC0                0x000C
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#define SYS_OSC1                0x0010
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#define SYS_OSC2                0x0014
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#define SYS_OSC3                0x0018
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#define SYS_OSC4                0x001C
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#define SYS_LOCK                0x0020
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#define SYS_100HZ               0x0024
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#define SYS_CFGDATA0            0x0028
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#define SYS_CFGDATA1            0x002C
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#define SYS_FLAGS               0x0030
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#define SYS_FLAGS_SET           0x0030
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#define SYS_FLAGS_CLR           0x0034
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#define SYS_NVFLAGS             0x0038
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#define SYS_NVFLAGS_SET         0x0038
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#define SYS_NVFLAGS_CLR         0x003C
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#define SYS_PCICTL              0x0044
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#define SYS_MCI                 0x0048
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#define SYS_FLASH               0x004C
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#define SYS_CLCD                0x0050
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#define SYS_CLCDSER             0x0054
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#define SYS_BOOTCS              0x0058
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#define SYS_24MHZ               0x005C
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#define SYS_MISC                0x0060
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#define SYS_DMAPSR0             0x0064
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#define SYS_DMAPSR1             0x0068
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#define SYS_DMAPSR2             0x006C
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#define SYS_IOSEL               0x0070
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#define SYS_PLDCTL1             0x0074
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#define SYS_PLDCTL2             0x0078
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#define SYS_BUSID               0x0080
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#define SYS_PROCID1             0x0084
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#define SYS_PROCID0             0x0088
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#define SYS_OSCRESET0           0x008C
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#define SYS_OSCRESET1           0x0090
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#define SYS_OSCRESET2           0x0094
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#define SYS_OSCRESET3           0x0098
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#define SYS_OSCRESET4           0x009C
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/* System Controller Lock/Unlock */
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#define SYSCTRL_LOCK            0xFF
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#define SYSCTRL_UNLOCK          0xA05F
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#define ID_MASK_REV             0xF0000000
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#define ID_MASK_HBI             0x0FFF0000
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#define ID_MASK_BUILD           0x0000F000
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#define ID_MASK_ARCH            0x00000F00
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#define ID_MASK_FPGA            0x000000FF
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#define SW_MASK_BOOTSEL         0x0000FF00
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#define SW_MASK_GP              0x000000FF
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#define LED_MASK_LED            0x000000FF
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#define FLASH_WRITE_EN          0x1
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#define FLASH_WRITE_DIS         0x0
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#define CLCD_QVGA               (0 << 8) /* 320x240 */
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#define CLDE_VGA                (1 << 8) /* 640x480 */
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#define CLCD_SMALL              (2 << 8) /* 220x176 */
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#define CLCD_SSP_CS             (1 << 7) /* SSP Chip Select */
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#define CLCD_TS_EN              (1 << 6) /* Touch Screen Enable */
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/* Different Voltages */
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#define CLCD_NEG_EN             (1 << 5)
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#define CLCD_3V5V_EN            (1 << 4)
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#define CLCD_POS_EN             (1 << 3)
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#define CLCD_IO_ON              (1 << 2)
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/* Normal without DCC, no FIQ, recommended for SMP */
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#define PLD_CTRL1_INTMOD_WITHOUT_DCC    (1 << 22)
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/* Not Recommended */
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#define PLD_CTRL1_INTMOD_WITH_DCC       (2 << 22)
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/* For single cpu such as 1136 */
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#define PLD_CTRL1_INTMOD_LEGACY         (4 << 22)
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#endif  /* __EB_SYSCTRL_H__ */

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