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drasko |
/*
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* low-level mmu operations
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*
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* Copyright (C) 2007 Bahadir Balban
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*/
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#include INC_ARCH(asm.h)
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#define C15_id c0
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#define C15_control c1
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#define C15_ttb c2
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#define C15_dom c3
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#define C15_fsr c5
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#define C15_far c6
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#define C15_tlb c8
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#define C15_C0_M 0x0001 /* MMU */
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#define C15_C0_A 0x0002 /* Alignment */
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#define C15_C0_C 0x0004 /* (D) Cache */
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#define C15_C0_W 0x0008 /* Write buffer */
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#define C15_C0_B 0x0080 /* Endianness */
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#define C15_C0_S 0x0100 /* System */
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#define C15_C0_R 0x0200 /* ROM */
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#define C15_C0_Z 0x0800 /* Branch Prediction */
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#define C15_C0_I 0x1000 /* I cache */
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#define C15_C0_V 0x2000 /* High vectors */
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/* FIXME: Make sure the ops that need r0 dont trash r0, or if they do,
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* save it on stack before these operations.
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*/
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/*
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* In ARM terminology, flushing the cache means invalidating its contents.
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* Cleaning the cache means, writing the contents of the cache back to
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* main memory. In write-back caches the cache must be cleaned before
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* flushing otherwise in-cache data is lost.
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*/
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BEGIN_PROC(arm_set_ttb)
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mcr p15, 0, r0, C15_ttb, c0, 0
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mov pc, lr
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END_PROC(arm_set_ttb)
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BEGIN_PROC(arm_get_domain)
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mrc p15, 0, r0, C15_dom, c0, 0
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mov pc, lr
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END_PROC(arm_get_domain)
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BEGIN_PROC(arm_set_domain)
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mcr p15, 0, r0, C15_dom, c0, 0
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mov pc, lr
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END_PROC(arm_set_domain)
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BEGIN_PROC(arm_enable_mmu)
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mrc p15, 0, r0, C15_control, c0, 0
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orr r0, r0, #C15_C0_M
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mcr p15, 0, r0, C15_control, c0, 0
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mov pc, lr
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END_PROC(arm_enable_mmu)
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BEGIN_PROC(arm_enable_icache)
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mrc p15, 0, r0, C15_control, c0, 0
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orr r0, r0, #C15_C0_I
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mcr p15, 0, r0, C15_control, c0, 0
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mov pc, lr
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END_PROC(arm_enable_icache)
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BEGIN_PROC(arm_enable_dcache)
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mrc p15, 0, r0, C15_control, c0, 0
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orr r0, r0, #C15_C0_C
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mcr p15, 0, r0, C15_control, c0, 0
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mov pc, lr
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END_PROC(arm_enable_dcache)
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BEGIN_PROC(arm_enable_wbuffer)
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mrc p15, 0, r0, C15_control, c0, 0
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orr r0, r0, #C15_C0_W
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mcr p15, 0, r0, C15_control, c0, 0
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mov pc, lr
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END_PROC(arm_enable_wbuffer)
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BEGIN_PROC(arm_enable_high_vectors)
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mrc p15, 0, r0, C15_control, c0, 0
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orr r0, r0, #C15_C0_V
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mcr p15, 0, r0, C15_control, c0, 0
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mov pc, lr
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END_PROC(arm_enable_high_vectors)
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BEGIN_PROC(arm_invalidate_cache)
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mov r0, #0 @ FIX THIS
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mcr p15, 0, r0, c7, c7 @ Flush I cache and D cache
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mov pc, lr
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END_PROC(arm_invalidate_cache)
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BEGIN_PROC(arm_invalidate_icache)
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mov r0, #0 @ FIX THIS
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mcr p15, 0, r0, c7, c5, 0 @ Flush I cache
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mov pc, lr
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END_PROC(arm_invalidate_icache)
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BEGIN_PROC(arm_invalidate_dcache)
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mov r0, #0 @ FIX THIS
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mcr p15, 0, r0, c7, c6, 0 @ Flush D cache
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mov pc, lr
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END_PROC(arm_invalidate_dcache)
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BEGIN_PROC(arm_clean_dcache)
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mrc p15, 0 , pc, c7, c10, 3 @ Test/clean dcache line
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bne arm_clean_dcache
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mcr p15, 0, ip, c7, c10, 4 @ Drain WB
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mov pc, lr
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END_PROC(arm_clean_dcache)
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BEGIN_PROC(arm_clean_invalidate_dcache)
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1:
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mrc p15, 0, pc, c7, c14, 3 @ Test/clean/flush dcache line
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@ COMMENT: Why use PC?
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bne 1b
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mcr p15, 0, ip, c7, c10, 4 @ Drain WB
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mov pc, lr
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END_PROC(arm_clean_invalidate_dcache)
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BEGIN_PROC(arm_clean_invalidate_cache)
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1:
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mrc p15, 0, r15, c7, c14, 3 @ Test/clean/flush dcache line
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@ COMMENT: Why use PC?
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bne 1b
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mcr p15, 0, ip, c7, c5, 0 @ Flush icache
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mcr p15, 0, ip, c7, c10, 4 @ Drain WB
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mov pc, lr
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END_PROC(arm_clean_invalidate_cache)
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BEGIN_PROC(arm_drain_writebuffer)
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mov r0, #0 @ FIX THIS
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mcr p15, 0, r0, c7, c10, 4
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mov pc, lr
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END_PROC(arm_drain_writebuffer)
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BEGIN_PROC(arm_invalidate_tlb)
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mcr p15, 0, ip, c8, c7
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mov pc, lr
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END_PROC(arm_invalidate_tlb)
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BEGIN_PROC(arm_invalidate_itlb)
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mov r0, #0 @ FIX THIS
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mcr p15, 0, r0, c8, c5, 0
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mov pc, lr
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END_PROC(arm_invalidate_itlb)
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BEGIN_PROC(arm_invalidate_dtlb)
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mov r0, #0 @ FIX THIS
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mcr p15, 0, r0, c8, c6, 0
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mov pc, lr
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END_PROC(arm_invalidate_dtlb)
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