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[/] [c0or1k/] [trunk/] [src/] [drivers/] [irq/] [gic/] [gic.c] - Blame information for rev 2

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1 2 drasko 
/*
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 * Generic Interrupt Controller support.
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 *
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 * Copyright (C) 2009-2010 B Labs Ltd.
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 *
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 * Authors: Prem Mallappa, Bahadir Balban
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 */
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#include <l4/lib/bit.h>
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#include <l4/lib/printk.h>
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#include <l4/generic/irq.h>
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#include INC_PLAT(irq.h)
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#include INC_SUBARCH(mmu_ops.h)
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#include <l4/drivers/irq/gic/gic.h>
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#include <l4/generic/smp.h>
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#define GIC_ACK_IRQ_MASK                0x1FF
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#define GIC_ACK_CPU_MASK                0xE00
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#define GIC_IRQ_SPURIOUS                0x3FF
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volatile struct gic_data gic_data[IRQ_CHIPS_MAX];
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static inline struct gic_data *get_gic_data(l4id_t irq)
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{
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        volatile struct irq_chip *chip = irq_desc_array[irq].chip;
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        if (chip)
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                return (struct gic_data *)chip->data;
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        else
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                return 0;
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}
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/* Returns the irq number on this chip converting the irq bitvector */
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l4id_t gic_read_irq(void *data)
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{
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        volatile struct gic_data *gic = (struct gic_data *)data;
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        l4id_t irq = gic->cpu->ack;
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        /* This is an IPI - EOI it here, since it requires cpu field */
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        if ((irq & GIC_ACK_IRQ_MASK) < 16) {
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                gic_eoi_irq(irq);
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                /* Get the actual irq number */
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                irq &= GIC_ACK_IRQ_MASK;
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        }
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        /* Detect GIC spurious magic value and return generic one */
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        if (irq == GIC_IRQ_SPURIOUS)
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                return IRQ_SPURIOUS;
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        return irq;
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}
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void gic_mask_irq(l4id_t irq)
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{
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        volatile struct gic_data *gic = get_gic_data(irq);
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        u32 offset = irq >> 5; /* irq / 32 */
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        gic->dist->clr_en[offset] = 1 << (irq % 32);
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}
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void gic_unmask_irq(l4id_t irq)
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{
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        volatile struct gic_data *gic = get_gic_data(irq);
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        u32 offset = irq >> 5 ; /* irq / 32 */
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        gic->dist->set_en[offset] = 1 << (irq % 32);
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}
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void gic_eoi_irq(l4id_t irq)
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{
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        /* Careful, irq may have cpu field encoded */
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        volatile struct gic_data *gic =
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                get_gic_data(irq & GIC_ACK_IRQ_MASK);
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        gic->cpu->eoi = irq;
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}
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void gic_ack_and_mask(l4id_t irq)
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{
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        //printk("disable/eoi irq %d\n", irq);
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        gic_mask_irq(irq);
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        gic_eoi_irq(irq);
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}
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void gic_set_pending(l4id_t irq)
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{
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        volatile struct gic_data *gic = get_gic_data(irq);
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        u32 offset = irq >> 5; /* irq / 32 */
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        gic->dist->set_pending[offset] = 1 << (irq % 32);
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}
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void gic_clear_pending(l4id_t irq)
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{
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        volatile struct gic_data *gic = get_gic_data(irq);
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        u32 offset = irq >> 5; /* irq / 32 */
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        gic->dist->clr_pending[offset] = 1 << (irq % 32);
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}
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void gic_cpu_init(int idx, unsigned long base)
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{
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        volatile struct gic_cpu *cpu;
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        gic_data[idx].cpu = (struct gic_cpu *)base;
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        cpu = gic_data[idx].cpu;
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        /* Disable */
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        cpu->control = 0;
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        /* Set */
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        cpu->prio_mask = 0xf0;
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        cpu->bin_point = 3;
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        /* Enable */
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        cpu->control = 1;
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}
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void gic_dist_init(int idx, unsigned long base)
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{
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        volatile struct gic_dist *dist;
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        int irqs_per_word;
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        int nirqs;
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        gic_data[idx].dist = (struct gic_dist *)(base);
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        dist = gic_data[idx].dist;
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        /* Disable gic */
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        dist->control = 0;
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        /* 32*(N+1) interrupts supported */
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        nirqs = 32 * ((dist->type & 0x1f) + 1);
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        if (nirqs > IRQS_MAX)
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                nirqs = IRQS_MAX;
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        /* Disable all interrupts */
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        irqs_per_word = 32;
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        for (int i = 0; i < nirqs; i += irqs_per_word)
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                dist->clr_en[i/irqs_per_word] = 0xffffffff;
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        /* Clear all pending interrupts */
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        for (int i = 0; i < nirqs; i += irqs_per_word)
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                dist->clr_pending[i/irqs_per_word] = 0xffffffff;
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        /* Set all irqs as normal priority, 8 bits per interrupt */
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        irqs_per_word = 4;
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        for (int i = 32; i < nirqs; i += irqs_per_word)
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                dist->priority[i/irqs_per_word] = 0xa0a0a0a0;
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        /* Set all target to cpu0, 8 bits per interrupt */
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        for (int i = 32; i < nirqs; i += irqs_per_word)
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                dist->target[i/irqs_per_word] = 0x01010101;
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        /* Configure all to be level-sensitive, 2 bits per interrupt */
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        irqs_per_word = 16;
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        for (int i = 32; i < nirqs; i += irqs_per_word)
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                dist->config[i/irqs_per_word] = 0x00000000;
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        /* Enable GIC Distributor */
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        dist->control = 1;
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}
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/* Some functions, may be helpful */
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void gic_set_target(l4id_t irq, u32 cpu)
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{
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        volatile struct gic_data *gic = get_gic_data(irq);
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        u32 offset = irq >> 2; /* irq / 4 */
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        if (cpu > 1) {
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                printk("Setting irqs to reach multiple cpu targets requires a"
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                       "lock on the irq controller\n"
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                       "GIC is a racy hardware in this respect\n");
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                BUG();
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        }
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        gic->dist->target[offset] |= (cpu << ((irq % 4) * 8));
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}
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u32 gic_get_target(u32 irq)
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{
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        volatile struct gic_data *gic = get_gic_data(irq);
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        u32 offset = irq >> 2; /* irq / 4 */
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        unsigned int target = gic->dist->target[offset];
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        BUG_ON(irq > 0xFF);
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        target >>= ((irq % 4) * 8);
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        return target & 0xFF;
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}
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void gic_set_priority(u32 irq, u32 prio)
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{
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        volatile struct gic_data *gic = get_gic_data(irq);
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        u32 offset = irq >> 3; /* irq / 8 */
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        BUG_ON(prio > 0xF);
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        BUG_ON(irq > 0xFF);
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        /* target = cpu << ((irq % 4) * 4) */
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        gic->dist->target[offset] |= (prio << (irq & 0x1C));
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}
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u32 gic_get_priority(u32 irq)
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{
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        volatile struct gic_data *gic = get_gic_data(irq);
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        u32 offset = irq >> 3; /* offset = irq / 8 */
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        u32 prio = gic->dist->target[offset] & (irq & 0xFC);
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        return prio;
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}
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#define IPI_CPU_SHIFT   16
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void gic_send_ipi(int cpumask, int ipi_cmd)
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{
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        volatile struct gic_dist *dist = gic_data[0].dist;
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        unsigned int ipi_word = (cpumask << IPI_CPU_SHIFT) | ipi_cmd;
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        dist->soft_int = ipi_word;
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}
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void gic_print_cpu()
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{
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        volatile struct gic_cpu *cpu = gic_data[0].cpu;
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        printk("GIC CPU%d highest pending: %d\n", smp_get_cpuid(), cpu->high_pending);
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        printk("GIC CPU%d running: %d\n", smp_get_cpuid(), cpu->running);
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}
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/* Make the generic code happy */
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void gic_dummy_init()
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{
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}

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