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drasko |
/*
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* omap GP timer driver honoring generic
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* timer library API
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*
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* Copyright (C) 2010 B Labs Ltd.
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*
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* Author: Bahadir Balban
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*/
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#include <l4/drivers/timer/omap/timer.h>
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#include INC_ARCH(io.h)
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#define OMAP_TIMER_MAT_IT_FLAG (1 << 0)
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#define OMAP_TIMER_OVR_IT_FLAG (1 << 1)
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#define OMAP_TIMER_TCAR_IT_FLAG (1 << 2)
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void timer_irq_clear(unsigned long timer_base)
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{
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volatile u32 reg = read(timer_base + OMAP_TIMER_TISR);
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reg |= OMAP_TIMER_OVR_IT_FLAG;
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write(reg, timer_base + OMAP_TIMER_TISR);
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}
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u32 timer_periodic_intr_status(unsigned long timer_base)
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{
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volatile u32 reg = read(timer_base + OMAP_TIMER_TISR);
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return (reg & OMAP_TIMER_OVR_IT_FLAG);
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}
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#define OMAP_TIMER_SOFT_RESET (1 << 1)
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void timer_reset(unsigned long timer_base)
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{
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/* Reset Timer */
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write(OMAP_TIMER_SOFT_RESET, timer_base + OMAP_TIMER_TIOCP);
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/* Wait for reset completion */
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while (!read(timer_base + OMAP_TIMER_TSTAT));
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}
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void timer_load(unsigned long timer_base, u32 value)
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{
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write(value, timer_base + OMAP_TIMER_TLDR);
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write(value, timer_base + OMAP_TIMER_TCRR);
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}
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u32 timer_read(unsigned long timer_base)
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{
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return read(timer_base + OMAP_TIMER_TCRR);
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}
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#define OMAP_TIMER_START (1 << 0)
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void timer_start(unsigned long timer_base)
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{
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volatile u32 reg = read(timer_base + OMAP_TIMER_TCLR);
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reg |= OMAP_TIMER_START;
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write(reg, timer_base + OMAP_TIMER_TCLR);
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}
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void timer_stop(unsigned long timer_base)
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{
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volatile u32 reg = read(timer_base + OMAP_TIMER_TCLR);
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reg &= (~OMAP_TIMER_START);
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write(reg, timer_base + OMAP_TIMER_TCLR);
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}
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/*
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* Beagle Board RevC manual:
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* overflow period = (0xffffffff - TLDR + 1)*PS*(1/TIMER_FCLK)
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* where,
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* PS: Prescaler divisor (we are not using this)
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*
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* Beagle board manual says, 26MHz oscillator present on board.
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* U-Boot divides the sys_clock by 2 if sys_clk is >19MHz,
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* so,we have sys_clk frequency = 13MHz
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*
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* TIMER_FCLK = 13MHz
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*
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*/
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void timer_init_oneshot(unsigned long timer_base)
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{
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volatile u32 reg;
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/* Reset the timer */
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timer_reset(timer_base);
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/* Set timer to compare mode */
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reg = read(timer_base + OMAP_TIMER_TCLR);
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reg |= (1 << OMAP_TIMER_MODE_COMPARE);
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write(reg, timer_base + OMAP_TIMER_TCLR);
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write(0xffffffff, timer_base + OMAP_TIMER_TMAR);
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/* Clear pending Interrupts, if any */
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write(7, timer_base + OMAP_TIMER_TISR);
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}
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void timer_init_periodic(unsigned long timer_base)
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{
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volatile u32 reg;
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/* Reset the timer */
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timer_reset(timer_base);
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/* Set timer to autoreload mode */
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reg = read(timer_base + OMAP_TIMER_TCLR);
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reg |= (1 << OMAP_TIMER_MODE_AUTORELAOD);
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write(reg, timer_base + OMAP_TIMER_TCLR);
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/*
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* Beagle Board RevC manual:
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* overflow period = (0xffffffff - TLDR + 1)*PS*(1/TIMER_FCLK)
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* where,
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* PS: Prescaler divisor (we are not using this)
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*
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* Beagle board manual says, 26MHz oscillator present on board.
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* U-Boot divides the sys_clock by 2 if sys_clk is >19MHz,
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* so,we have sys_clk frequency = 13MHz
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*
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* TIMER_FCLK = 13MHz
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* So, for 1ms period, TLDR = 0xffffcd38
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*
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*/
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timer_load(timer_base, 0xffffcd38);
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/* Clear pending Interrupts, if any */
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write(7, timer_base + OMAP_TIMER_TISR);
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/* Enable inteerupts */
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write((1 << OMAP_TIMER_INTR_OVERFLOW), timer_base + OMAP_TIMER_TIER);
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}
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void timer_init(unsigned long timer_base)
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{
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timer_init_periodic(timer_base);
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}
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