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drasko |
/*
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* EB platform-specific initialisation and setup
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*
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* Copyright (C) 2009 B Labs Ltd.
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*/
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#include <l4/generic/platform.h>
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#include <l4/generic/bootmem.h>
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#include INC_PLAT(offsets.h)
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#include INC_ARCH(io.h)
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#include <l4/generic/space.h>
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#include <l4/generic/irq.h>
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#include <l4/generic/cap-types.h>
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#include INC_PLAT(platform.h)
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#include INC_PLAT(irq.h)
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#include INC_GLUE(mapping.h)
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/*
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* The devices that are used by the kernel are mapped
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* independent of these capabilities, but these provide a
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* concise description of what is used by the kernel.
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*/
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int platform_setup_device_caps(struct kernel_resources *kres)
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{
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#if 0
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struct capability *uart[4], *timer[4];
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/* Setup capabilities for userspace uarts and timers */
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uart[1] = alloc_bootmem(sizeof(*uart[1]), 0);
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uart[1]->start = __pfn(PLATFORM_UART1_BASE);
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uart[1]->end = uart[1]->start + 1;
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uart[1]->size = uart[1]->end - uart[1]->start;
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cap_set_devtype(uart[1], CAP_DEVTYPE_UART);
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cap_set_devnum(uart[1], 1);
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link_init(&uart[1]->list);
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cap_list_insert(uart[1], &kres->devmem_free);
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uart[2] = alloc_bootmem(sizeof(*uart[2]), 0);
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uart[2]->start = __pfn(PLATFORM_UART2_BASE);
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uart[2]->end = uart[2]->start + 1;
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uart[2]->size = uart[2]->end - uart[2]->start;
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cap_set_devtype(uart[2], CAP_DEVTYPE_UART);
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cap_set_devnum(uart[2], 2);
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link_init(&uart[2]->list);
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cap_list_insert(uart[2], &kres->devmem_free);
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uart[3] = alloc_bootmem(sizeof(*uart[3]), 0);
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uart[3]->start = __pfn(PLATFORM_UART3_BASE);
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uart[3]->end = uart[3]->start + 1;
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uart[3]->size = uart[3]->end - uart[3]->start;
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cap_set_devtype(uart[3], CAP_DEVTYPE_UART);
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cap_set_devnum(uart[3], 3);
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link_init(&uart[3]->list);
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cap_list_insert(uart[3], &kres->devmem_free);
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/* Setup timer1 capability as free */
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timer[1] = alloc_bootmem(sizeof(*timer[1]), 0);
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timer[1]->start = __pfn(PLATFORM_TIMER1_BASE);
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timer[1]->end = timer[1]->start + 1;
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timer[1]->size = timer[1]->end - timer[1]->start;
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cap_set_devtype(timer[1], CAP_DEVTYPE_TIMER);
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cap_set_devnum(timer[1], 1);
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link_init(&timer[1]->list);
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cap_list_insert(timer[1], &kres->devmem_free);
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#endif
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return 0;
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}
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void init_platform_irq_controller()
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{
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#if 0
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unsigned int sysctrl = PLATFORM_SYSCTRL_VBASE;
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write(SYSCTRL_UNLOCK, sysctrl + SYS_LOCK);
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write(PLD_CTRL1_INTMOD_WITHOUT_DCC, sysctrl+SYS_PLDCTL1);
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write(SYSCTRL_LOCK, sysctrl + SYS_LOCK); /* Lock again */
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#ifdef CONFIG_CPU_ARM11MPCORE
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/* TODO: we need to map 64KB ?*/
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add_boot_mapping(ARM11MP_PRIVATE_MEM_BASE, EB_MPCORE_PRIV_MEM_VBASE,
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PAGE_SIZE*2, MAP_IO_DEFAULT);
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gic_dist_init(0, GIC0_DIST_VBASE);
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gic_cpu_init(0, GIC0_CPU_VBASE);
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#endif
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add_boot_mapping(PLATFORM_GIC1_BASE, PLATFORM_GIC1_VBASE, PAGE_SIZE*2,
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MAP_IO_DEFAULT);
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gic_dist_init(1, GIC1_DIST_VBASE);
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gic_cpu_init(1, PLATFORM_GIC1_VBASE);
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irq_controllers_init();
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#endif
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}
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void init_platform_devices()
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{
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}
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