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[/] [cachecontroller/] [trunk/] [rtl/] [verilog/] [bufif0_8bit.v] - Blame information for rev 3

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1 3 chinthakaa
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company: 
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// Engineer: Chinthaka A.K.
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// 
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// Create Date:    10:52:01 12/08/2009 
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// Design Name: 
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// Module Name:    bufif0_8bit 
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// Project Name: 
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// Target Devices: 
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// Tool versions: 
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// Description: 
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//
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// Dependencies: 
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//
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// Revision: 
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// Revision 0.01 - File Created
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// Additional Comments: 
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//
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//////////////////////////////////////////////////////////////////////////////////
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module bufif0_8bit(buf_out, buf_in,ENB);
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        output [7:0]buf_out;
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        input [7:0]buf_in;
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        input ENB;
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   bufif0(buf_out[0],buf_in[0],ENB);
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   bufif0(buf_out[1],buf_in[1],ENB);
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   bufif0(buf_out[2],buf_in[2],ENB);
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   bufif0(buf_out[3],buf_in[3],ENB);
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   bufif0(buf_out[4],buf_in[4],ENB);
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   bufif0(buf_out[5],buf_in[5],ENB);
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   bufif0(buf_out[6],buf_in[6],ENB);
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   bufif0(buf_out[7],buf_in[7],ENB);
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endmodule

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