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[/] [cachecontroller/] [trunk/] [rtl/] [verilog/] [eight_to_one_mux_8bit.v] - Blame information for rev 3

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1 3 chinthakaa
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company: 
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// Engineer: Chinthaka A.K
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// 
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// Create Date:    10:30:11 12/07/2009 
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// Design Name: 
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// Module Name:    eight_to_one_mux_8bit 
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// Project Name: 
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// Target Devices: 
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// Tool versions: 
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// Description: 
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//
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// Dependencies: 
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//
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// Revision: 
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// Revision 0.01 - File Created
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// Additional Comments: 
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//
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//////////////////////////////////////////////////////////////////////////////////
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module eight_to_one_mux_8bit(mux_out,mux_in,select);
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        output reg[7:0] mux_out;
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        input [63:0]mux_in;
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        input [2:0]select;
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        always @(select, mux_in)
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                        case(select)
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                                3'b000:mux_out <= mux_in[7:0];
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                                3'b001:mux_out <= mux_in[15:8];
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                                3'b010:mux_out <= mux_in[23:16];
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                                3'b011:mux_out <= mux_in[31:24];
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                                3'b100:mux_out <= mux_in[39:32];
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                                3'b101:mux_out <= mux_in[47:40];
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                                3'b110:mux_out <= mux_in[55:48];
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                                3'b111:mux_out <= mux_in[63:56];
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                        endcase
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endmodule
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