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1 2 jt_eaton
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   <meta http-equiv="CONTENT-TYPE" content="text/html; charset=utf-8">
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   <title>start</title>
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   <meta name="date" content="2008-01-08T12:01:41-0500">
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 <h1><a name="cde_sram_dp"></a>SOCGEN Datasheet:<br>
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     <p style="margin-bottom: 0in;"><a href="#cde_sram_dp">cde_sram_dp<br>
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     </a></p>
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 <br>
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 <br>  Synchronous two-port ram with seperate read/write ports
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 <br>
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       <li>
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         <p><a href="../src/cde_sram_dp.v">SourceCode <br>
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         </a></p>
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       <li>
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         <p style="margin-bottom: 0in;"><a href="#Parameters">Parameters<br>
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         <p style="margin-bottom: 0in;"><a href="#Interface">Interface<br>
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         <p style="margin-bottom: 0in;"><a href="#Children">Children<br>
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         <p><a href="../../html/cde_sram_dp.html#TheoryofOperation">Theory of Operation<br>
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       </li>
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     </ul>
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   </li>
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 <img style="width: 683px; height: 278px;" alt=""  src="../png/cde_sram_dp_sym.png"><br>
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 <h2><b><a name="Parameters"></a>Parameters<br></b></h2>
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      <td style="vertical-align: top;">Name<br>      </td>
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      <td style="vertical-align: top;">default <br>      </td>
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      <td style="vertical-align: top;">Description<br></td>
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      <td style="vertical-align: top;">ADDR<br>      </td>
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          <td style="vertical-align: top;">0<br>      </td>
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          <td style="vertical-align: top;">Number of address bits<br></td>
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         </tr>
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      <td style="vertical-align: top;">WIDTH<br>      </td>
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          <td style="vertical-align: top;">0<br>      </td>
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          <td style="vertical-align: top;">Number of data bits<br></td>
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      <td style="vertical-align: top;">WORDS<br>      </td>
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          <td style="vertical-align: top;">0<br>      </td>
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          <td style="vertical-align: top;">Number of memory words. Must be fully addressable by ADDR address bits<br></td>
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      <td style="vertical-align: top;">WRITETHRU<br>      </td>
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          <td style="vertical-align: top;">0<br>      </td>
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          <td style="vertical-align: top;">If a read and write occur to the same address on the same cycle then 0 reads old data while 1 reads new<br></td>
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      <td style="vertical-align: top;">DEFAULT<br>      </td>
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          <td style="vertical-align: top;">{WIDTH{1'bx}}<br>      </td>
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          <td style="vertical-align: top;">Output read value if cs and rd are not both active <br></td>
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      <td style="vertical-align: top;">INIT_FILE<br>      </td>
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          <td style="vertical-align: top;">"NONE"<br>      </td>
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          <td style="vertical-align: top;">Filename of memory image loaded at startup<br></td>
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      <td style="vertical-align: top;">INSTANCE_NAME<br>      </td>
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          <td style="vertical-align: top;">"U1"<br>      </td>
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          <td style="vertical-align: top;">Instance name of sram. Only needed for asic tool flows<br></td>
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 <h2><b><b><a name="Interface"></a>Interface</b><b>&nbsp;<br>
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       <td style="vertical-align: top;">NAME<br>      </td>
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       <td style="vertical-align: top;">Type<br>      </td>
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       <td style="vertical-align: top;">Description<br>      </td>
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     <tr>
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        <td style="vertical-align: top;">clk<br>      </td>
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       <td style="vertical-align: top;">input<br>      </td>
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       <td style="vertical-align: top;">Active high clock<br>      </td>
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        <td style="vertical-align: top;">cs<br>      </td>
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       <td style="vertical-align: top;">input<br>      </td>
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       <td style="vertical-align: top;">Active high chip select<br>      </td>
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        <td style="vertical-align: top;">raddr[ADDR-1:0 ]<br>      </td>
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       <td style="vertical-align: top;">input<br>      </td>
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       <td style="vertical-align: top;">Memory read address bits<br>      </td>
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        <td style="vertical-align: top;">rd<br>      </td>
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       <td style="vertical-align: top;">input<br>      </td>
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       <td style="vertical-align: top;">Active high read enable<br>      </td>
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        <td style="vertical-align: top;">rdata[WIDTH-1:0 ]<br>      </td>
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       <td style="vertical-align: top;">output<br>      </td>
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       <td style="vertical-align: top;">read data out<br>      </td>
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        <td style="vertical-align: top;">waddr[ADDR-1:0 ]<br>      </td>
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       <td style="vertical-align: top;">input<br>      </td>
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       <td style="vertical-align: top;">Memory write address bits<br>      </td>
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        <td style="vertical-align: top;">wdata[WIDTH-1:0 ]<br>      </td>
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       <td style="vertical-align: top;">input<br>      </td>
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       <td style="vertical-align: top;">write data in<br>      </td>
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        <td style="vertical-align: top;">wr<br>      </td>
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       <td style="vertical-align: top;">input<br>      </td>
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       <td style="vertical-align: top;">Active high write enable<br>      </td>
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      <td style="vertical-align: top;">Instance<br>      </td>
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      <td style="vertical-align: top;">Vendor<br>      </td>
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      <td style="vertical-align: top;">Library<br></td>
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      <td style="vertical-align: top;">Component<br></td>
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      <td style="vertical-align: top;">Version<br></td>
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