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---------------------------------------------------------------------------------------------------
--
-- Title       : cfft
-- Design      : cfft
-- Author      : ZHAO Ming
-- email        : sradio@opencores.org
--
---------------------------------------------------------------------------------------------------
--
-- File        : cfft.vhd
-- Generated   : Thu Oct  3 03:03:58 2002
--
---------------------------------------------------------------------------------------------------
--
-- Description : radix 4 1024 point FFT input 12 bit Output 14 bit with 
--               limit and overfall processing internal
--
--              The gain is 0.0287 for FFT and 29.4 for IFFT
--
--                              The output is 4-based reversed ordered, it means
--                              a0a1a2a3a4a5a6a7a8a9 => a8a9a6a7a4a5aa2a3a0a1
--                              
--
---------------------------------------------------------------------------------------------------
 
 
---------------------------------------------------------------------------------------------------
--
-- port :
--                      clk : main clk          -- I have test 90M with Xilinx virtex600E
--          rst : globe reset   -- '1' for reset
--                      start : start fft       -- one clock '1' before data input
--                      invert : '0' for fft and '1' for ifft, it is sampled when start is '1' 
--                      Iin,Qin : data input-- following start immediately, input data
--                              -- power should not be too big
--          inputbusy : if it change to '0' then next fft is enable
--                      outdataen : when it is '1', the valid data is output
--          Iout,Qout : fft data output when outdataen is '1'                                                                      
--
---------------------------------------------------------------------------------------------------
--
-- Revisions       :    0
-- Revision Number :    1
-- Version         :    1.1.0
-- Date            :    Oct 17 2002
-- Modifier        :    ZHAO Ming 
-- Desccription    :    Data width configurable 
--
---------------------------------------------------------------------------------------------------
--
-- Revisions       :    0
-- Revision Number :    2
-- Version         :    1.2.0
-- Date            :    Oct 18 2002
-- Modifier        :    ZHAO Ming 
-- Desccription    :    Point configurable
--                      FFT Gain                IFFT GAIN
--                               256    0.0698                  17.9
--                              1024    0.0287                  29.4
--                              4096    0.0118                  48.2742
--                   
--
---------------------------------------------------------------------------------------------------
--
-- Revisions       :    0
-- Revision Number :    3
-- Version         :    1.3.0
-- Date            :    Nov 19 2002
-- Modifier        :    ZHAO Ming 
-- Desccription    :    add output data position indication 
--                   
--
---------------------------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
 
entity cfft is
        generic (
                WIDTH : Natural;
                POINT : Natural;
                STAGE : Natural   -- STAGE=log4(POINT)
        );
         port(
                 clk : in STD_LOGIC;
                 rst : in STD_LOGIC;
                 start : in STD_LOGIC;
                 invert : in std_logic;
                 Iin : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
                 Qin : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
                 inputbusy : out STD_LOGIC;
                 outdataen : out STD_LOGIC;
                 Iout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0);
                 Qout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0);
                 OutPosition : out STD_LOGIC_VECTOR( 2*STAGE-1 downto 0 )
             );
end cfft;
 
 
architecture cfft of cfft is
 
component address
        generic (
                WIDTH : Natural;
                POINT : Natural;
                STAGE : Natural
        );
         port(
                 clk : in STD_LOGIC;
                 rst : in STD_LOGIC;
                 start : in STD_LOGIC;
                 Iin : in std_logic_vector( WIDTH-1 downto 0 );
                 Qin : in std_logic_vector( WIDTH-1 downto 0 );
                 fftI : in std_logic_vector( WIDTH-1 downto 0 );
                 fftQ : in std_logic_vector( WIDTH-1 downto 0 );
                 wdataI : out std_logic_vector( WIDTH-1 downto 0 );
                 wdataQ : out std_logic_vector( WIDTH-1 downto 0 );
                 raddr : out STD_LOGIC_VECTOR(2*STAGE-1 downto 0);
                 waddr : out STD_LOGIC_VECTOR(2*STAGE-1 downto 0);
                 wen : out std_logic;
                 factorstart : out STD_LOGIC;
                 cfft4start : out STD_LOGIC;
                 outdataen : out std_logic;
                 inputbusy : out std_logic;
             OutPosition : out STD_LOGIC_VECTOR( 2*STAGE-1 downto 0 )
                 );
end component;
 
component blockdram
generic(
        depth:  integer;
        Dwidth: integer;
        Awidth: integer
);
port(
        addra: IN std_logic_VECTOR(Awidth-1 downto 0);
        clka: IN std_logic;
        addrb: IN std_logic_VECTOR(Awidth-1 downto 0);
        clkb: IN std_logic;
        dia: IN std_logic_VECTOR(Dwidth-1 downto 0);
        wea: IN std_logic;
        dob: OUT std_logic_VECTOR(Dwidth-1 downto 0));
end component;
 
component cfft4
        generic (
                WIDTH : Natural
        );
         port(
                 clk : in STD_LOGIC;
                 rst : in STD_LOGIC;
                 start : in STD_LOGIC;
                 invert : in std_logic;
                 I : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
                 Q : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
                 Iout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0);
                 Qout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0)
             );
end component;
 
component div4limit
        generic (
                WIDTH : Natural
        );
        port(
                clk : in std_logic;
                 D : in STD_LOGIC_VECTOR(WIDTH+3 downto 0);
                 Q : out STD_LOGIC_VECTOR(WIDTH-1 downto 0)
             );
end component;
 
component mulfactor
        generic (
                WIDTH : Natural;
                STAGE : Natural
        );
         port(
                 clk : in STD_LOGIC;
                 rst : in STD_LOGIC;
                 angle : in signed(2*STAGE-1 downto 0);
                 I : in signed(WIDTH+1 downto 0);
                 Q : in signed(WIDTH+1 downto 0);
                 Iout : out signed(WIDTH+3 downto 0);
                 Qout : out signed(WIDTH+3 downto 0)
             );
end component;
 
component rofactor
        generic (
                POINT : Natural;
                STAGE : Natural
        );
         port(
                 clk : in STD_LOGIC;
                 rst : in STD_LOGIC;
                 start : in STD_LOGIC;
                 invert : in std_logic;
                 angle : out STD_LOGIC_VECTOR(2*STAGE-1 downto 0)
             );
end component;
signal wea,cfft4start,factorstart:std_logic:='0';
signal wdataI,wdataQ,fftI,fftQ,Iramout,Qramout:std_logic_vector(WIDTH-1 downto 0):=(others=>'0');
signal waddr,raddr:std_logic_vector( 2*STAGE-1 downto 0):=(others=>'0');
signal Icfft4out,Qcfft4out:std_logic_vector( WIDTH+1 downto 0):=(others=>'0');
signal angle:std_logic_vector( 2*STAGE-1 downto 0 ):=( others=>'0');
signal Imulout,Qmulout:signed( WIDTH+3 downto 0):=(others=>'0');
signal inv_reg:std_logic:='0';
 
begin
 
Aaddress:address
generic map (
        WIDTH=>WIDTH,
        POINT=>POINT,
        STAGE=>STAGE
)
port map (
        clk=>clk,
        rst=>rst,
        start=>start,
        Iin=>Iin,
        Qin=>Qin,
        fftI=>fftI,
        fftQ=>fftQ,
        wdataI=>wdataI,
        wdataQ=>wdataQ,
        raddr=>raddr,
        waddr=>waddr,
        wen=>wea,
        factorstart=>factorstart,
        cfft4start=>cfft4start,
        outdataen=>outdataen,
        inputbusy=>inputbusy,
        OutPosition=>OutPosition
             );
 
Iram:blockdram
generic map (
        depth=>POINT,
        Dwidth=>WIDTH,
        Awidth=>2*STAGE
)
port map (
        addra=>waddr,
        clka=>clk,
        addrb=>raddr,
        clkb=>clk,
        dia=>wdataI,
        wea=>wea,
        dob=>Iramout
);
 
Qram:blockdram
generic map (
        depth=>POINT,
        Dwidth=>WIDTH,
        Awidth=>2*STAGE
)
port map (
        addra=>waddr,
        clka=>clk,
        addrb=>raddr,
        clkb=>clk,
        dia=>wdataQ,
        wea=>wea,
        dob=>Qramout
);
 
acfft4:cfft4
generic map (
        WIDTH=>WIDTH
)
port map (
        clk=>clk,
        rst=>rst,
        start=>cfft4start,
        invert=>inv_reg,
        I=>Iramout,
        Q=>Qramout,
        Iout=>Icfft4out,
        Qout=>Qcfft4out
             );
 
Iout<=Icfft4out;
Qout<=Qcfft4out;
 
Ilimit:div4limit
generic map (
        WIDTH=>WIDTH
)
port map (
        clk=>clk,
        D=>std_logic_vector(Imulout),
        Q=>fftI
             );
Qlimit:div4limit
generic map (
        WIDTH=>WIDTH
)
port map (
        clk=>clk,
        D=>std_logic_vector(Qmulout),
        Q=>fftQ
             );
 
amulfactor:mulfactor
generic map (
        WIDTH=>WIDTH,
        STAGE=>STAGE
)
port map (
        clk=>clk,
        rst=>rst,
        angle=>signed(angle),
        I=>signed(Icfft4out),
        Q=>signed(Qcfft4out),
        Iout=>Imulout,
        Qout=>Qmulout
             );
 
arofactor:rofactor
generic map (
        POINT=>POINT,
        STAGE=>STAGE
)
port map (
        clk=>clk,
        rst=>rst,
        start=>factorstart,
        invert=>inv_reg,
        angle=>angle
             );
 
process( clk, rst )
begin
        if rst='1' then
                inv_reg<='0';
        elsif clk'event and clk='1' then
                if start='1' then
                        inv_reg<=invert;
                end if;
        end if;
end process;
 
 
 
end cfft;

Line No.	Rev	Author	Line
1	2	sradio	`---------------------------------------------------------------------------------------------------`
2			`--`
3			`-- Title : cfft`
4			`-- Design : cfft`
5			`-- Author : ZHAO Ming`
6			`-- email : sradio@opencores.org`
7			`--`
8			`---------------------------------------------------------------------------------------------------`
9			`--`
10			`-- File : cfft.vhd`
11			`-- Generated : Thu Oct 3 03:03:58 2002`
12			`--`
13			`---------------------------------------------------------------------------------------------------`
14			`--`
15	3	sradio	`-- Description : radix 4 1024 point FFT input 12 bit Output 14 bit with`
16	2	sradio	`-- limit and overfall processing internal`
17			`--`
18			`-- The gain is 0.0287 for FFT and 29.4 for IFFT`
19			`--`
20			`-- The output is 4-based reversed ordered, it means`
21			`-- a0a1a2a3a4a5a6a7a8a9 => a8a9a6a7a4a5aa2a3a0a1`
22			`--`
23			`--`
24			`---------------------------------------------------------------------------------------------------`
25
26
27			`---------------------------------------------------------------------------------------------------`
28			`--`
29			`-- port :`
30			`-- clk : main clk -- I have test 90M with Xilinx virtex600E`
31			`-- rst : globe reset -- '1' for reset`
32			`-- start : start fft -- one clock '1' before data input`
33	13	sradio	`-- invert : '0' for fft and '1' for ifft, it is sampled when start is '1'`
34	2	sradio	`-- Iin,Qin : data input-- following start immediately, input data`
35			`-- -- power should not be too big`
36			`-- inputbusy : if it change to '0' then next fft is enable`
37			`-- outdataen : when it is '1', the valid data is output`
38			`-- Iout,Qout : fft data output when outdataen is '1'`
39			`--`
40			`---------------------------------------------------------------------------------------------------`
41			`--`
42			`-- Revisions : 0`
43			`-- Revision Number : 1`
44			`-- Version : 1.1.0`
45			`-- Date : Oct 17 2002`
46			`-- Modifier : ZHAO Ming`
47			`-- Desccription : Data width configurable`
48			`--`
49			`---------------------------------------------------------------------------------------------------`
50			`--`
51			`-- Revisions : 0`
52			`-- Revision Number : 2`
53			`-- Version : 1.2.0`
54			`-- Date : Oct 18 2002`
55			`-- Modifier : ZHAO Ming`
56			`-- Desccription : Point configurable`
57			`-- FFT Gain IFFT GAIN`
58			`-- 256 0.0698 17.9`
59			`-- 1024 0.0287 29.4`
60			`-- 4096 0.0118 48.2742`
61			`--`
62			`--`
63			`---------------------------------------------------------------------------------------------------`
64	9	sradio	`--`
65			`-- Revisions : 0`
66			`-- Revision Number : 3`
67			`-- Version : 1.3.0`
68			`-- Date : Nov 19 2002`
69			`-- Modifier : ZHAO Ming`
70			`-- Desccription : add output data position indication`
71			`--`
72			`--`
73			`---------------------------------------------------------------------------------------------------`
74	2	sradio
75			`library IEEE;`
76			`use IEEE.STD_LOGIC_1164.all;`
77			`use IEEE.STD_LOGIC_ARITH.all;`
78
79			`entity cfft is`
80			`generic (`
81			`WIDTH : Natural;`
82			`POINT : Natural;`
83			`STAGE : Natural -- STAGE=log4(POINT)`
84			`);`
85			`port(`
86			`clk : in STD_LOGIC;`
87			`rst : in STD_LOGIC;`
88			`start : in STD_LOGIC;`
89	13	sradio	`invert : in std_logic;`
90	2	sradio	`Iin : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);`
91			`Qin : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);`
92			`inputbusy : out STD_LOGIC;`
93			`outdataen : out STD_LOGIC;`
94			`Iout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0);`
95	9	sradio	`Qout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0);`
96			`OutPosition : out STD_LOGIC_VECTOR( 2*STAGE-1 downto 0 )`
97	2	sradio	`);`
98			`end cfft;`
99
100
101			`architecture cfft of cfft is`
102
103			`component address`
104			`generic (`
105			`WIDTH : Natural;`
106			`POINT : Natural;`
107			`STAGE : Natural`
108			`);`
109			`port(`
110			`clk : in STD_LOGIC;`
111			`rst : in STD_LOGIC;`
112			`start : in STD_LOGIC;`
113			`Iin : in std_logic_vector( WIDTH-1 downto 0 );`
114			`Qin : in std_logic_vector( WIDTH-1 downto 0 );`
115			`fftI : in std_logic_vector( WIDTH-1 downto 0 );`
116			`fftQ : in std_logic_vector( WIDTH-1 downto 0 );`
117			`wdataI : out std_logic_vector( WIDTH-1 downto 0 );`
118			`wdataQ : out std_logic_vector( WIDTH-1 downto 0 );`
119			`raddr : out STD_LOGIC_VECTOR(2*STAGE-1 downto 0);`
120			`waddr : out STD_LOGIC_VECTOR(2*STAGE-1 downto 0);`
121			`wen : out std_logic;`
122			`factorstart : out STD_LOGIC;`
123			`cfft4start : out STD_LOGIC;`
124			`outdataen : out std_logic;`
125	9	sradio	`inputbusy : out std_logic;`
126			`OutPosition : out STD_LOGIC_VECTOR( 2*STAGE-1 downto 0 )`
127			`);`
128	2	sradio	`end component;`
129
130			`component blockdram`
131			`generic(`
132			`depth: integer;`
133			`Dwidth: integer;`
134			`Awidth: integer`
135			`);`
136			`port(`
137			`addra: IN std_logic_VECTOR(Awidth-1 downto 0);`
138			`clka: IN std_logic;`
139			`addrb: IN std_logic_VECTOR(Awidth-1 downto 0);`
140			`clkb: IN std_logic;`
141			`dia: IN std_logic_VECTOR(Dwidth-1 downto 0);`
142			`wea: IN std_logic;`
143			`dob: OUT std_logic_VECTOR(Dwidth-1 downto 0));`
144			`end component;`
145
146			`component cfft4`
147			`generic (`
148			`WIDTH : Natural`
149			`);`
150			`port(`
151			`clk : in STD_LOGIC;`
152			`rst : in STD_LOGIC;`
153			`start : in STD_LOGIC;`
154	13	sradio	`invert : in std_logic;`
155	2	sradio	`I : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);`
156			`Q : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);`
157			`Iout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0);`
158			`Qout : out STD_LOGIC_VECTOR(WIDTH+1 downto 0)`
159			`);`
160			`end component;`
161
162			`component div4limit`
163			`generic (`
164			`WIDTH : Natural`
165			`);`
166			`port(`
167			`clk : in std_logic;`
168			`D : in STD_LOGIC_VECTOR(WIDTH+3 downto 0);`
169			`Q : out STD_LOGIC_VECTOR(WIDTH-1 downto 0)`
170			`);`
171			`end component;`
172
173			`component mulfactor`
174			`generic (`
175			`WIDTH : Natural;`
176			`STAGE : Natural`
177			`);`
178			`port(`
179			`clk : in STD_LOGIC;`
180			`rst : in STD_LOGIC;`
181			`angle : in signed(2*STAGE-1 downto 0);`
182			`I : in signed(WIDTH+1 downto 0);`
183			`Q : in signed(WIDTH+1 downto 0);`
184			`Iout : out signed(WIDTH+3 downto 0);`
185			`Qout : out signed(WIDTH+3 downto 0)`
186			`);`
187			`end component;`
188
189			`component rofactor`
190			`generic (`
191			`POINT : Natural;`
192			`STAGE : Natural`
193			`);`
194			`port(`
195			`clk : in STD_LOGIC;`
196			`rst : in STD_LOGIC;`
197			`start : in STD_LOGIC;`
198	13	sradio	`invert : in std_logic;`
199	2	sradio	`angle : out STD_LOGIC_VECTOR(2*STAGE-1 downto 0)`
200			`);`
201			`end component;`
202			`signal wea,cfft4start,factorstart:std_logic:='0';`
203			`signal wdataI,wdataQ,fftI,fftQ,Iramout,Qramout:std_logic_vector(WIDTH-1 downto 0):=(others=>'0');`
204			`signal waddr,raddr:std_logic_vector( 2*STAGE-1 downto 0):=(others=>'0');`
205			`signal Icfft4out,Qcfft4out:std_logic_vector( WIDTH+1 downto 0):=(others=>'0');`
206			`signal angle:std_logic_vector( 2*STAGE-1 downto 0 ):=( others=>'0');`
207			`signal Imulout,Qmulout:signed( WIDTH+3 downto 0):=(others=>'0');`
208			`signal inv_reg:std_logic:='0';`
209
210			`begin`
211
212			`Aaddress:address`
213			`generic map (`
214			`WIDTH=>WIDTH,`
215			`POINT=>POINT,`
216			`STAGE=>STAGE`
217			`)`
218			`port map (`
219			`clk=>clk,`
220			`rst=>rst,`
221			`start=>start,`
222			`Iin=>Iin,`
223			`Qin=>Qin,`
224			`fftI=>fftI,`
225			`fftQ=>fftQ,`
226			`wdataI=>wdataI,`
227			`wdataQ=>wdataQ,`
228			`raddr=>raddr,`
229			`waddr=>waddr,`
230			`wen=>wea,`
231			`factorstart=>factorstart,`
232			`cfft4start=>cfft4start,`
233			`outdataen=>outdataen,`
234	9	sradio	`inputbusy=>inputbusy,`
235			`OutPosition=>OutPosition`
236	2	sradio	`);`
237
238			`Iram:blockdram`
239			`generic map (`
240			`depth=>POINT,`
241			`Dwidth=>WIDTH,`
242			`Awidth=>2*STAGE`
243			`)`
244			`port map (`
245			`addra=>waddr,`
246			`clka=>clk,`
247			`addrb=>raddr,`
248			`clkb=>clk,`
249			`dia=>wdataI,`
250			`wea=>wea,`
251			`dob=>Iramout`
252			`);`
253
254			`Qram:blockdram`
255			`generic map (`
256			`depth=>POINT,`
257			`Dwidth=>WIDTH,`
258			`Awidth=>2*STAGE`
259			`)`
260			`port map (`
261			`addra=>waddr,`
262			`clka=>clk,`
263			`addrb=>raddr,`
264			`clkb=>clk,`
265			`dia=>wdataQ,`
266			`wea=>wea,`
267			`dob=>Qramout`
268			`);`
269
270			`acfft4:cfft4`
271			`generic map (`
272			`WIDTH=>WIDTH`
273			`)`
274			`port map (`
275			`clk=>clk,`
276			`rst=>rst,`
277			`start=>cfft4start,`
278	13	sradio	`invert=>inv_reg,`
279	2	sradio	`I=>Iramout,`
280			`Q=>Qramout,`
281			`Iout=>Icfft4out,`
282			`Qout=>Qcfft4out`
283			`);`
284
285			`Iout<=Icfft4out;`
286			`Qout<=Qcfft4out;`
287
288			`Ilimit:div4limit`
289			`generic map (`
290			`WIDTH=>WIDTH`
291			`)`
292			`port map (`
293			`clk=>clk,`
294			`D=>std_logic_vector(Imulout),`
295			`Q=>fftI`
296			`);`
297			`Qlimit:div4limit`
298			`generic map (`
299			`WIDTH=>WIDTH`
300			`)`
301			`port map (`
302			`clk=>clk,`
303			`D=>std_logic_vector(Qmulout),`
304			`Q=>fftQ`
305			`);`
306
307			`amulfactor:mulfactor`
308			`generic map (`
309			`WIDTH=>WIDTH,`
310			`STAGE=>STAGE`
311			`)`
312			`port map (`
313			`clk=>clk,`
314			`rst=>rst,`
315			`angle=>signed(angle),`
316			`I=>signed(Icfft4out),`
317			`Q=>signed(Qcfft4out),`
318			`Iout=>Imulout,`
319			`Qout=>Qmulout`
320			`);`
321
322			`arofactor:rofactor`
323			`generic map (`
324			`POINT=>POINT,`
325			`STAGE=>STAGE`
326			`)`
327			`port map (`
328			`clk=>clk,`
329			`rst=>rst,`
330			`start=>factorstart,`
331	13	sradio	`invert=>inv_reg,`
332	2	sradio	`angle=>angle`
333			`);`
334
335			`process( clk, rst )`
336			`begin`
337			`if rst='1' then`
338			`inv_reg<='0';`
339			`elsif clk'event and clk='1' then`
340			`if start='1' then`
341	13	sradio	`inv_reg<=invert;`
342	2	sradio	`end if;`
343			`end if;`
344			`end process;`
345
346
347
348			`end cfft;`

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[/] [cfft/] [trunk/] [src/] [cfft.vhd] - Blame information for rev 14