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[/] [cfi_ctrl/] [trunk/] [bench/] [verilog/] [cfi_ctrl_wb_bench.v] - Blame information for rev 2

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/* Testbench of Wishbone classic-slave wrapped basic CFI controller */
 
`include "def.h"
`include "data.h"
 
`timescale 1ns/1ps
 
module cfi_ctrl_wb_bench();
 
 
  // Signal Bus
  wire [`ADDRBUS_dim - 1:0] A;         // Address Bus 
  wire [`DATABUS_dim - 1:0] DQ;        // Data I/0 Bus
  // Control Signal
  wire WE_N;                            // Write Enable 
  wire OE_N;                            // Output Enable
  wire CE_N;                            // Chip Enable
  wire RST_N;                           // Reset
  wire WP_N;                           // Write Protect
  wire ADV_N;                            // Latch Enable
  wire CLK;                              // Clock
  wire WAIT;                           // Wait
 
  // Voltage signal rappresentad by integer Vector which correspond to millivolts
  wire [`Voltage_range] VCC;  // Supply Voltage
  wire [`Voltage_range] VCCQ; // Supply Voltage for I/O Buffers
  wire [`Voltage_range] VPP; // Optional Supply Voltage for Fast Program & Erase  
 
  //wire STS;
 
  wire Info;      // Activate/Deactivate info device operation
assign Info = 1;
assign VCC = 36'd1700;
assign VCCQ = 36'd1700;
assign VPP = 36'd2000;
 
parameter sys_clk_half_period = 15.15/2; /* 66MHz */
parameter sys_clk_period = sys_clk_half_period*2;
   reg sys_clk;
   reg sys_rst;
 
initial begin
   sys_clk  = 0;
   forever
      #sys_clk_half_period sys_clk  = ~sys_clk;
end
 
initial begin
   sys_rst  = 1;
   #sys_clk_period;
   #sys_clk_period;
   sys_rst  = 0;
end
 
   reg [31:0] wb_adr_i;
   reg [31:0] wb_dat_i;
   reg        wb_stb_i;
   reg        wb_cyc_i;
   reg [3:0]  wb_sel_i;
   reg        wb_we_i;
   wire [31:0] wb_dat_o;
   wire        wb_ack_o;
 
   task wb_wait_for_ack;
      begin
         while (!wb_ack_o)
           #sys_clk_period;
 
         wb_stb_i = 0;
         wb_cyc_i = 0;
         /* Leave these deasserted for a cycle */
         #sys_clk_period;
      end
   endtask // wb_wait_for_ack
 
   task wb_write_16bits;
      input [31:0] address;
      input [15:0] dat;
      begin
         wb_adr_i = {address[31:1],1'b0};
         wb_dat_i = {dat,dat};
         wb_sel_i = address[1] ? 4'h3 : 4'hc;
         wb_we_i = 1;
         wb_stb_i = 1;
         wb_cyc_i = 1;
         #sys_clk_period;
         wb_wait_for_ack();
      end
   endtask // wb_write_16bits
 
 
   task wb_write_32bits;
      input [31:0] address;
      input [31:0] dat;
      begin
         wb_adr_i = address;
         wb_dat_i = dat;
         wb_sel_i = 4'hf;
         wb_we_i = 1;
         wb_stb_i = 1;
         wb_cyc_i = 1;
         #sys_clk_period;
         wb_wait_for_ack();
      end
   endtask // wb_write_32bits
 
   task wb_read_8bits;
      input [31:0] address;
      output [7:0] dat;
      begin
         wb_adr_i = address[31:0];
         wb_sel_i = address[1:0] == 2'b00 ? 4'h8 :
                    address[1:0] == 2'b01 ? 4'h4 :
                    address[1:0] == 2'b10 ? 4'h2 : 4'h1;
         wb_we_i = 0;
         wb_stb_i = 1;
         wb_cyc_i = 1;
         #sys_clk_period;
         wb_wait_for_ack();
         dat = address[1:0] == 2'b00 ? wb_dat_o[31:24] :
               address[1:0] == 2'b01 ? wb_dat_o[23:16] :
               address[1:0] == 2'b10 ? wb_dat_o[15:8]  : wb_dat_o[7:0];
      end
   endtask // wb_read_16bits
 
   task wb_read_16bits;
      input [31:0] address;
      output [15:0] dat;
      begin
         wb_adr_i = {address[31:1],1'b0};
         wb_sel_i = address[1] ? 4'h3 : 4'hc;
         wb_we_i = 0;
         wb_stb_i = 1;
         wb_cyc_i = 1;
         #sys_clk_period;
         wb_wait_for_ack();
         dat = address[1] ? wb_dat_o[15:0] : wb_dat_o[31:16];
      end
   endtask // wb_read_16bits
 
   task wb_read_32bits;
      input [31:0] address;
      output [31:0] dat;
      begin
         wb_adr_i = address;
         wb_sel_i = 4'hf;
         wb_we_i = 0;
         wb_stb_i = 1;
         wb_cyc_i = 1;
         #sys_clk_period;
         wb_wait_for_ack();
         dat = wb_dat_o;
      end
   endtask // wb_read_32bits
 
   reg [31:0] temp_data;
   reg [7:0]  status_reg;
 
   task wb_cfi_read_status_reg;
      output [7:0] stat;
      begin
         wb_write_16bits(32'h0, 16'h0070);
         wb_read_16bits(32'h0, stat);
      end
   endtask // wb_cfi_read_status_reg
 
   task wb_cfi_wait_for_status_ready;
      begin
         wb_cfi_read_status_reg(status_reg);
         while (!status_reg[7])
           wb_cfi_read_status_reg(status_reg);
      end
   endtask // wb_cfi_wait_for_status_ready
 
   task wb_cfi_write_16bits;
      input [31:0] address;
      input [15:0] dat;
       begin
          wb_write_16bits(address, 16'h0040);
          wb_write_16bits(address, dat);
          wb_cfi_wait_for_status_ready();
       end
   endtask // wb_cfi_write_16bits
 
   task wb_cfi_write_32bits;
      input [31:0] address;
      input [31:0] dat;
      begin
         wb_cfi_write_16bits(address, dat[31:16]);
         wb_cfi_write_16bits(address+2, dat[15:0]);
      end
   endtask // wb_cfi_write_32bits
 
   task wb_cfi_read_8bits;
      input [31:0] address;
      output [7:0] dat;
      begin
         wb_write_16bits(address, 16'h00ff);
         wb_read_8bits(address, dat);
      end
   endtask // wb_read_8bits
 
   task wb_cfi_read_16bits;
      input [31:0] address;
      output [15:0] dat;
       begin
          wb_write_16bits(address, 16'h00ff);
          wb_read_16bits(address, dat);
       end
   endtask // wb_cfi_read_16bits
 
   task wb_cfi_read_32bits;
      input [31:0] address;
      output [31:0] dat;
      begin
         wb_cfi_read_16bits(address, dat[31:16]);
         wb_cfi_read_16bits(address+2, dat[15:0]);
      end
   endtask // wb_cfi_write_32bits
 
   task wb_cfi_unlock_and_erase_block;
      input [31:0] address;
      begin
         /* Unlock block */
         wb_write_16bits(address, 16'h0060);
         wb_write_16bits(address, 16'h00D0);
         /* Erase block */
         wb_write_16bits(address, 16'h0020);
         wb_write_16bits(address, 16'h00D0);
         wb_cfi_wait_for_status_ready();
      end
   endtask
 
   task wb_cfi_read_device_ident;
      input [31:0] address;
      output [15:0] data;
      begin
         wb_write_16bits(32'd0, 16'h0090);
         wb_read_16bits((address<<1), data);
      end
   endtask // wb_cfi_read_device_ident
 
   task wb_cfi_query;
      input [31:0] address;
      output [15:0] data;
      begin
         wb_write_16bits(32'd0, 16'h0098);
         wb_read_16bits((address<<1), data);
      end
   endtask // wb_cfi_query
 
   task wb_cfi_read_all_device_ident;
      begin
         $display("%t Reading device identifier information", $time);
         wb_cfi_read_device_ident(0,temp_data[15:0]);
         $display("%t Manufacturer code: %04h",$time,temp_data[15:0]);
         wb_cfi_read_device_ident(31'h1,temp_data[15:0]);
         $display("%t Device ID code: %04h",$time,temp_data[15:0]);
         wb_cfi_read_device_ident(31'h5,temp_data[15:0]);
         $display("%t RCR: %04h",$time,temp_data[15:0]);
         wb_cfi_read_device_ident(31'h2 + ((128*1024)>>1),temp_data[15:0]);
         $display("%t Block 0 locked?: %04h",$time,temp_data[15:0]);
      end
   endtask // wb_cfi_read_all_device_ident
 
   task wb_cfi_queries;
      begin
         $display("%t Querying CFI device", $time);
         wb_cfi_query(31'h10,temp_data[15:0]);
         $display("%t Query ID string: %04h",$time,temp_data[15:0]);
         wb_cfi_query(31'h13,temp_data[15:0]);
         $display("%t Vendor command set and control interface ID: %04h",$time,temp_data[15:0]);
         wb_cfi_query(31'h27,temp_data[15:0]);
         $display("%t size 2^n: %04h",$time,temp_data[15:0]);
         wb_cfi_query(31'h28,temp_data[15:0]);
         $display("%t device interface code: %04h",$time,temp_data[15:0]);
         wb_cfi_query(31'h2c,temp_data[15:0]);
         $display("%t number of erase block regions: %04h",$time,temp_data[15:0]);
 
      end
      endtask
 
   integer i;
 
   parameter test_length = 16;
   reg [31:0] temp_result;
 
 /* Main test stimulus block */
initial begin
 
   wb_adr_i = 0;
   wb_dat_i = 0;
   wb_stb_i = 0;
   wb_cyc_i = 0;
   wb_sel_i = 0;
   wb_we_i = 0;
 
   $dumpfile("../out/cfi_ctrl_wb_bench.vcd");
   $dumpvars(0);
   $display("Starting CFI Wishbone controller test");
   #550; // Wait for the part to power up
 
 
   wb_cfi_read_all_device_ident();
   #500;
   wb_cfi_queries();
   #500;
 
   /* Ready first block for play*/
   wb_cfi_unlock_and_erase_block(0);
 
   /* Clear status register */
   wb_write_16bits(32'd0, 16'h0050);
 
   /* Write a 32-bit word */
   wb_cfi_write_32bits(32'h0000_0000, 32'hdeadbeef);
 
   /* read it back */
   wb_cfi_read_32bits(32'h0000_0000, temp_data);
   /* works because we're already in read array mode */
   wb_read_32bits(32'h0000_0000, temp_data);
 
   /* Write data  */
   for (i = 0; i< ((4*test_length)/4); i=i+1) begin
      temp_result[31:16] = 16'hdead-i;
      temp_result[15:0] = 16'hbeef+i;
      wb_cfi_write_32bits(32'h0000_0000+i*4, temp_result);
   end
 
   /* Read it back 16-bits at a time and check it */
   for (i = 0; i< ((4*test_length)/4); i=i+1) begin
      wb_cfi_read_16bits(32'h0000_0000+i*4, temp_data[31:16]);
      wb_cfi_read_16bits(32'h0000_0000+i*4+2, temp_data[15:0]);
      temp_result[31:16] = 16'hdead-i;
      temp_result[15:0] = 16'hbeef+i;
      if (temp_data != temp_result) begin
         $display("Read verify error at %h",(i*4));
         $finish;
      end
   end
   /* Read it back 8-bits at a time and check it */
   for (i = 0; i< ((4*test_length)/4); i=i+1) begin
      wb_read_8bits(32'h0000_0000+i*4, temp_data[31:24]);
      wb_read_8bits(32'h0000_0000+i*4+1, temp_data[23:16]);
      wb_read_8bits(32'h0000_0000+i*4+2, temp_data[15:8]);
      wb_read_8bits(32'h0000_0000+i*4+3, temp_data[7:0]);
      temp_result[31:16] = 16'hdead-i;
      temp_result[15:0] = 16'hbeef+i;
      if (temp_data != temp_result) begin
         $display("Read verify error at %h",(i*4));
         $finish;
      end
   end
 
   /* Read it back and check it */
   for (i = 0; i< ((4*test_length)/4); i=i+1) begin
      wb_read_32bits(32'h0000_0000+i*4, temp_data);
      temp_result[31:16] = 16'hdead-i;
      temp_result[15:0] = 16'hbeef+i;
      if (temp_data != temp_result) begin
         $display("Read verify error at %h",(i*4));
         $finish;
      end
   end
 
   /* Test doing things on next block */
   wb_cfi_unlock_and_erase_block(32'h20000);
 
   /* Write 4k of data  */
   for (i = 0; i< ((4*test_length)/4); i=i+1) begin
      temp_result[31:16] = 16'hdead-i;
      temp_result[15:0] = 16'hbeef+i;
      wb_cfi_write_32bits(32'h0002_0000+i*4, temp_result);
   end
   /* Read it back and check it */
   /* Do one read to get it into the read array mode */
   wb_cfi_read_16bits(32'h0002_0000, temp_data[15:0]);
   for (i = 0; i< ((4*test_length)/4); i=i+1) begin
      wb_read_32bits(32'h0002_0000+i*4, temp_data);
      temp_result[31:16] = 16'hdead-i;
      temp_result[15:0] = 16'hbeef+i;
      if (temp_data != temp_result) begin
        $display("Read verify error at %h",(i*4));
         $finish;
      end
   end
 
   /* Read it back 16-bits at a time and check it */
   for (i = 0; i< ((4*test_length)/4); i=i+1) begin
      wb_read_16bits(32'h0002_0000+i*4, temp_data[31:16]);
      wb_read_16bits(32'h0002_0000+i*4+2, temp_data[15:0]);
      temp_result[31:16] = 16'hdead-i;
      temp_result[15:0] = 16'hbeef+i;
      if (temp_data != temp_result) begin
         $display("Read verify error at %h",(i*4));
         $finish;
      end
   end
 
   $display("Finishing CFI Wishbone controller test");
   $finish;
end
 
/* timeout function - sim shouldn't run much longer than this */
/*
initial begin
   #55000;
   $display("Simulation finish due to timeout");
   $finish;
end
*/
cfi_ctrl
  #(.cfi_engine("DISABLED")) /* Simpler controller */
  dut
   (
    .wb_clk_i(sys_clk),
    .wb_rst_i(sys_rst),
 
    .wb_adr_i(wb_adr_i),
    .wb_dat_i(wb_dat_i),
    .wb_stb_i(wb_stb_i),
    .wb_cyc_i(wb_cyc_i),
    .wb_we_i (wb_we_i ),
    .wb_sel_i(wb_sel_i),
    .wb_dat_o(wb_dat_o),
    .wb_ack_o(wb_ack_o),
 
    .flash_dq_io(DQ),
    .flash_adr_o(A),
    .flash_adv_n_o(ADV_N),
    .flash_ce_n_o(CE_N),
    .flash_clk_o(CLK),
    .flash_oe_n_o(OE_N),
    .flash_rst_n_o(RST_N),
    .flash_wait_i(WAIT),
    .flash_we_n_o(WE_N),
    .flash_wp_n_o(WP_N)
    );
 
x28fxxxp30 part(A, DQ, WE_N, OE_N, CE_N, ADV_N, CLK,
                WAIT, WP_N, RST_N, VCC, VCCQ, VPP, Info);
 
 
endmodule

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Subversion Repositories cfi_ctrl

[/] [cfi_ctrl/] [trunk/] [bench/] [verilog/] [cfi_ctrl_wb_bench.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	julius	`/* Testbench of Wishbone classic-slave wrapped basic CFI controller */`
2
3			`include "def.h"
4			`include "data.h"
5
6			`timescale 1ns/1ps
7
8			`module cfi_ctrl_wb_bench();`
9
10
11			`// Signal Bus`
12			wire [`ADDRBUS_dim - 1:0] A; // Address Bus
13			wire [`DATABUS_dim - 1:0] DQ; // Data I/0 Bus
14			`// Control Signal`
15			`wire WE_N; // Write Enable`
16			`wire OE_N; // Output Enable`
17			`wire CE_N; // Chip Enable`
18			`wire RST_N; // Reset`
19			`wire WP_N; // Write Protect`
20			`wire ADV_N; // Latch Enable`
21			`wire CLK; // Clock`
22			`wire WAIT; // Wait`
23
24			`// Voltage signal rappresentad by integer Vector which correspond to millivolts`
25			wire [`Voltage_range] VCC; // Supply Voltage
26			wire [`Voltage_range] VCCQ; // Supply Voltage for I/O Buffers
27			wire [`Voltage_range] VPP; // Optional Supply Voltage for Fast Program & Erase
28
29			`//wire STS;`
30
31			`wire Info; // Activate/Deactivate info device operation`
32			`assign Info = 1;`
33			`assign VCC = 36'd1700;`
34			`assign VCCQ = 36'd1700;`
35			`assign VPP = 36'd2000;`
36
37			`parameter sys_clk_half_period = 15.15/2; /* 66MHz */`
38			`parameter sys_clk_period = sys_clk_half_period*2;`
39			`reg sys_clk;`
40			`reg sys_rst;`
41
42			`initial begin`
43			`sys_clk = 0;`
44			`forever`
45			`#sys_clk_half_period sys_clk = ~sys_clk;`
46			`end`
47
48			`initial begin`
49			`sys_rst = 1;`
50			`#sys_clk_period;`
51			`#sys_clk_period;`
52			`sys_rst = 0;`
53			`end`
54
55			`reg [31:0] wb_adr_i;`
56			`reg [31:0] wb_dat_i;`
57			`reg wb_stb_i;`
58			`reg wb_cyc_i;`
59			`reg [3:0] wb_sel_i;`
60			`reg wb_we_i;`
61			`wire [31:0] wb_dat_o;`
62			`wire wb_ack_o;`
63
64			`task wb_wait_for_ack;`
65			`begin`
66			`while (!wb_ack_o)`
67			`#sys_clk_period;`
68
69			`wb_stb_i = 0;`
70			`wb_cyc_i = 0;`
71			`/* Leave these deasserted for a cycle */`
72			`#sys_clk_period;`
73			`end`
74			`endtask // wb_wait_for_ack`
75
76			`task wb_write_16bits;`
77			`input [31:0] address;`
78			`input [15:0] dat;`
79			`begin`
80			`wb_adr_i = {address[31:1],1'b0};`
81			`wb_dat_i = {dat,dat};`
82			`wb_sel_i = address[1] ? 4'h3 : 4'hc;`
83			`wb_we_i = 1;`
84			`wb_stb_i = 1;`
85			`wb_cyc_i = 1;`
86			`#sys_clk_period;`
87			`wb_wait_for_ack();`
88			`end`
89			`endtask // wb_write_16bits`
90
91
92			`task wb_write_32bits;`
93			`input [31:0] address;`
94			`input [31:0] dat;`
95			`begin`
96			`wb_adr_i = address;`
97			`wb_dat_i = dat;`
98			`wb_sel_i = 4'hf;`
99			`wb_we_i = 1;`
100			`wb_stb_i = 1;`
101			`wb_cyc_i = 1;`
102			`#sys_clk_period;`
103			`wb_wait_for_ack();`
104			`end`
105			`endtask // wb_write_32bits`
106
107			`task wb_read_8bits;`
108			`input [31:0] address;`
109			`output [7:0] dat;`
110			`begin`
111			`wb_adr_i = address[31:0];`
112			`wb_sel_i = address[1:0] == 2'b00 ? 4'h8 :`
113			`address[1:0] == 2'b01 ? 4'h4 :`
114			`address[1:0] == 2'b10 ? 4'h2 : 4'h1;`
115			`wb_we_i = 0;`
116			`wb_stb_i = 1;`
117			`wb_cyc_i = 1;`
118			`#sys_clk_period;`
119			`wb_wait_for_ack();`
120			`dat = address[1:0] == 2'b00 ? wb_dat_o[31:24] :`
121			`address[1:0] == 2'b01 ? wb_dat_o[23:16] :`
122			`address[1:0] == 2'b10 ? wb_dat_o[15:8] : wb_dat_o[7:0];`
123			`end`
124			`endtask // wb_read_16bits`
125
126			`task wb_read_16bits;`
127			`input [31:0] address;`
128			`output [15:0] dat;`
129			`begin`
130			`wb_adr_i = {address[31:1],1'b0};`
131			`wb_sel_i = address[1] ? 4'h3 : 4'hc;`
132			`wb_we_i = 0;`
133			`wb_stb_i = 1;`
134			`wb_cyc_i = 1;`
135			`#sys_clk_period;`
136			`wb_wait_for_ack();`
137			`dat = address[1] ? wb_dat_o[15:0] : wb_dat_o[31:16];`
138			`end`
139			`endtask // wb_read_16bits`
140
141			`task wb_read_32bits;`
142			`input [31:0] address;`
143			`output [31:0] dat;`
144			`begin`
145			`wb_adr_i = address;`
146			`wb_sel_i = 4'hf;`
147			`wb_we_i = 0;`
148			`wb_stb_i = 1;`
149			`wb_cyc_i = 1;`
150			`#sys_clk_period;`
151			`wb_wait_for_ack();`
152			`dat = wb_dat_o;`
153			`end`
154			`endtask // wb_read_32bits`
155
156			`reg [31:0] temp_data;`
157			`reg [7:0] status_reg;`
158
159			`task wb_cfi_read_status_reg;`
160			`output [7:0] stat;`
161			`begin`
162			`wb_write_16bits(32'h0, 16'h0070);`
163			`wb_read_16bits(32'h0, stat);`
164			`end`
165			`endtask // wb_cfi_read_status_reg`
166
167			`task wb_cfi_wait_for_status_ready;`
168			`begin`
169			`wb_cfi_read_status_reg(status_reg);`
170			`while (!status_reg[7])`
171			`wb_cfi_read_status_reg(status_reg);`
172			`end`
173			`endtask // wb_cfi_wait_for_status_ready`
174
175			`task wb_cfi_write_16bits;`
176			`input [31:0] address;`
177			`input [15:0] dat;`
178			`begin`
179			`wb_write_16bits(address, 16'h0040);`
180			`wb_write_16bits(address, dat);`
181			`wb_cfi_wait_for_status_ready();`
182			`end`
183			`endtask // wb_cfi_write_16bits`
184
185			`task wb_cfi_write_32bits;`
186			`input [31:0] address;`
187			`input [31:0] dat;`
188			`begin`
189			`wb_cfi_write_16bits(address, dat[31:16]);`
190			`wb_cfi_write_16bits(address+2, dat[15:0]);`
191			`end`
192			`endtask // wb_cfi_write_32bits`
193
194			`task wb_cfi_read_8bits;`
195			`input [31:0] address;`
196			`output [7:0] dat;`
197			`begin`
198			`wb_write_16bits(address, 16'h00ff);`
199			`wb_read_8bits(address, dat);`
200			`end`
201			`endtask // wb_read_8bits`
202
203			`task wb_cfi_read_16bits;`
204			`input [31:0] address;`
205			`output [15:0] dat;`
206			`begin`
207			`wb_write_16bits(address, 16'h00ff);`
208			`wb_read_16bits(address, dat);`
209			`end`
210			`endtask // wb_cfi_read_16bits`
211
212			`task wb_cfi_read_32bits;`
213			`input [31:0] address;`
214			`output [31:0] dat;`
215			`begin`
216			`wb_cfi_read_16bits(address, dat[31:16]);`
217			`wb_cfi_read_16bits(address+2, dat[15:0]);`
218			`end`
219			`endtask // wb_cfi_write_32bits`
220
221			`task wb_cfi_unlock_and_erase_block;`
222			`input [31:0] address;`
223			`begin`
224			`/* Unlock block */`
225			`wb_write_16bits(address, 16'h0060);`
226			`wb_write_16bits(address, 16'h00D0);`
227			`/* Erase block */`
228			`wb_write_16bits(address, 16'h0020);`
229			`wb_write_16bits(address, 16'h00D0);`
230			`wb_cfi_wait_for_status_ready();`
231			`end`
232			`endtask`
233
234			`task wb_cfi_read_device_ident;`
235			`input [31:0] address;`
236			`output [15:0] data;`
237			`begin`
238			`wb_write_16bits(32'd0, 16'h0090);`
239			`wb_read_16bits((address<<1), data);`
240			`end`
241			`endtask // wb_cfi_read_device_ident`
242
243			`task wb_cfi_query;`
244			`input [31:0] address;`
245			`output [15:0] data;`
246			`begin`
247			`wb_write_16bits(32'd0, 16'h0098);`
248			`wb_read_16bits((address<<1), data);`
249			`end`
250			`endtask // wb_cfi_query`
251
252			`task wb_cfi_read_all_device_ident;`
253			`begin`
254			`$display("%t Reading device identifier information", $time);`
255			`wb_cfi_read_device_ident(0,temp_data[15:0]);`
256			`$display("%t Manufacturer code: %04h",$time,temp_data[15:0]);`
257			`wb_cfi_read_device_ident(31'h1,temp_data[15:0]);`
258			`$display("%t Device ID code: %04h",$time,temp_data[15:0]);`
259			`wb_cfi_read_device_ident(31'h5,temp_data[15:0]);`
260			`$display("%t RCR: %04h",$time,temp_data[15:0]);`
261			`wb_cfi_read_device_ident(31'h2 + ((128*1024)>>1),temp_data[15:0]);`
262			`$display("%t Block 0 locked?: %04h",$time,temp_data[15:0]);`
263			`end`
264			`endtask // wb_cfi_read_all_device_ident`
265
266			`task wb_cfi_queries;`
267			`begin`
268			`$display("%t Querying CFI device", $time);`
269			`wb_cfi_query(31'h10,temp_data[15:0]);`
270			`$display("%t Query ID string: %04h",$time,temp_data[15:0]);`
271			`wb_cfi_query(31'h13,temp_data[15:0]);`
272			`$display("%t Vendor command set and control interface ID: %04h",$time,temp_data[15:0]);`
273			`wb_cfi_query(31'h27,temp_data[15:0]);`
274			`$display("%t size 2^n: %04h",$time,temp_data[15:0]);`
275			`wb_cfi_query(31'h28,temp_data[15:0]);`
276			`$display("%t device interface code: %04h",$time,temp_data[15:0]);`
277			`wb_cfi_query(31'h2c,temp_data[15:0]);`
278			`$display("%t number of erase block regions: %04h",$time,temp_data[15:0]);`
279
280			`end`
281			`endtask`
282
283			`integer i;`
284
285			`parameter test_length = 16;`
286			`reg [31:0] temp_result;`
287
288			`/* Main test stimulus block */`
289			`initial begin`
290
291			`wb_adr_i = 0;`
292			`wb_dat_i = 0;`
293			`wb_stb_i = 0;`
294			`wb_cyc_i = 0;`
295			`wb_sel_i = 0;`
296			`wb_we_i = 0;`
297
298			`$dumpfile("../out/cfi_ctrl_wb_bench.vcd");`
299			`$dumpvars(0);`
300			`$display("Starting CFI Wishbone controller test");`
301			`#550; // Wait for the part to power up`
302
303
304			`wb_cfi_read_all_device_ident();`
305			`#500;`
306			`wb_cfi_queries();`
307			`#500;`
308
309			`/* Ready first block for play*/`
310			`wb_cfi_unlock_and_erase_block(0);`
311
312			`/* Clear status register */`
313			`wb_write_16bits(32'd0, 16'h0050);`
314
315			`/* Write a 32-bit word */`
316			`wb_cfi_write_32bits(32'h0000_0000, 32'hdeadbeef);`
317
318			`/* read it back */`
319			`wb_cfi_read_32bits(32'h0000_0000, temp_data);`
320			`/* works because we're already in read array mode */`
321			`wb_read_32bits(32'h0000_0000, temp_data);`
322
323			`/* Write data */`
324			`for (i = 0; i< ((4*test_length)/4); i=i+1) begin`
325			`temp_result[31:16] = 16'hdead-i;`
326			`temp_result[15:0] = 16'hbeef+i;`
327			`wb_cfi_write_32bits(32'h0000_0000+i*4, temp_result);`
328			`end`
329
330			`/* Read it back 16-bits at a time and check it */`
331			`for (i = 0; i< ((4*test_length)/4); i=i+1) begin`
332			`wb_cfi_read_16bits(32'h0000_0000+i*4, temp_data[31:16]);`
333			`wb_cfi_read_16bits(32'h0000_0000+i*4+2, temp_data[15:0]);`
334			`temp_result[31:16] = 16'hdead-i;`
335			`temp_result[15:0] = 16'hbeef+i;`
336			`if (temp_data != temp_result) begin`
337			`$display("Read verify error at %h",(i*4));`
338			`$finish;`
339			`end`
340			`end`
341			`/* Read it back 8-bits at a time and check it */`
342			`for (i = 0; i< ((4*test_length)/4); i=i+1) begin`
343			`wb_read_8bits(32'h0000_0000+i*4, temp_data[31:24]);`
344			`wb_read_8bits(32'h0000_0000+i*4+1, temp_data[23:16]);`
345			`wb_read_8bits(32'h0000_0000+i*4+2, temp_data[15:8]);`
346			`wb_read_8bits(32'h0000_0000+i*4+3, temp_data[7:0]);`
347			`temp_result[31:16] = 16'hdead-i;`
348			`temp_result[15:0] = 16'hbeef+i;`
349			`if (temp_data != temp_result) begin`
350			`$display("Read verify error at %h",(i*4));`
351			`$finish;`
352			`end`
353			`end`
354
355			`/* Read it back and check it */`
356			`for (i = 0; i< ((4*test_length)/4); i=i+1) begin`
357			`wb_read_32bits(32'h0000_0000+i*4, temp_data);`
358			`temp_result[31:16] = 16'hdead-i;`
359			`temp_result[15:0] = 16'hbeef+i;`
360			`if (temp_data != temp_result) begin`
361			`$display("Read verify error at %h",(i*4));`
362			`$finish;`
363			`end`
364			`end`
365
366			`/* Test doing things on next block */`
367			`wb_cfi_unlock_and_erase_block(32'h20000);`
368
369			`/* Write 4k of data */`
370			`for (i = 0; i< ((4*test_length)/4); i=i+1) begin`
371			`temp_result[31:16] = 16'hdead-i;`
372			`temp_result[15:0] = 16'hbeef+i;`
373			`wb_cfi_write_32bits(32'h0002_0000+i*4, temp_result);`
374			`end`
375			`/* Read it back and check it */`
376			`/* Do one read to get it into the read array mode */`
377			`wb_cfi_read_16bits(32'h0002_0000, temp_data[15:0]);`
378			`for (i = 0; i< ((4*test_length)/4); i=i+1) begin`
379			`wb_read_32bits(32'h0002_0000+i*4, temp_data);`
380			`temp_result[31:16] = 16'hdead-i;`
381			`temp_result[15:0] = 16'hbeef+i;`
382			`if (temp_data != temp_result) begin`
383			`$display("Read verify error at %h",(i*4));`
384			`$finish;`
385			`end`
386			`end`
387
388			`/* Read it back 16-bits at a time and check it */`
389			`for (i = 0; i< ((4*test_length)/4); i=i+1) begin`
390			`wb_read_16bits(32'h0002_0000+i*4, temp_data[31:16]);`
391			`wb_read_16bits(32'h0002_0000+i*4+2, temp_data[15:0]);`
392			`temp_result[31:16] = 16'hdead-i;`
393			`temp_result[15:0] = 16'hbeef+i;`
394			`if (temp_data != temp_result) begin`
395			`$display("Read verify error at %h",(i*4));`
396			`$finish;`
397			`end`
398			`end`
399
400			`$display("Finishing CFI Wishbone controller test");`
401			`$finish;`
402			`end`
403
404			`/* timeout function - sim shouldn't run much longer than this */`
405			`/*`
406			`initial begin`
407			`#55000;`
408			`$display("Simulation finish due to timeout");`
409			`$finish;`
410			`end`
411			`*/`
412			`cfi_ctrl`
413			`#(.cfi_engine("DISABLED")) /* Simpler controller */`
414			`dut`
415			`(`
416			`.wb_clk_i(sys_clk),`
417			`.wb_rst_i(sys_rst),`
418
419			`.wb_adr_i(wb_adr_i),`
420			`.wb_dat_i(wb_dat_i),`
421			`.wb_stb_i(wb_stb_i),`
422			`.wb_cyc_i(wb_cyc_i),`
423			`.wb_we_i (wb_we_i ),`
424			`.wb_sel_i(wb_sel_i),`
425			`.wb_dat_o(wb_dat_o),`
426			`.wb_ack_o(wb_ack_o),`
427
428			`.flash_dq_io(DQ),`
429			`.flash_adr_o(A),`
430			`.flash_adv_n_o(ADV_N),`
431			`.flash_ce_n_o(CE_N),`
432			`.flash_clk_o(CLK),`
433			`.flash_oe_n_o(OE_N),`
434			`.flash_rst_n_o(RST_N),`
435			`.flash_wait_i(WAIT),`
436			`.flash_we_n_o(WE_N),`
437			`.flash_wp_n_o(WP_N)`
438			`);`
439
440			`x28fxxxp30 part(A, DQ, WE_N, OE_N, CE_N, ADV_N, CLK,`
441			`WAIT, WP_N, RST_N, VCC, VCCQ, VPP, Info);`
442
443
444			`endmodule`