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[/] [cheap_ethernet/] [trunk/] [Ethernet_test/] [ipcore_dir/] [FIFORX.v] - Blame information for rev 3

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1 3 graver
/*******************************************************************************
2
*     This file is owned and controlled by Xilinx and must be used solely      *
3
*     for design, simulation, implementation and creation of design files      *
4
*     limited to Xilinx devices or technologies. Use with non-Xilinx           *
5
*     devices or technologies is expressly prohibited and immediately          *
6
*     terminates your license.                                                 *
7
*                                                                              *
8
*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY     *
9
*     FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY     *
10
*     PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE              *
11
*     IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS       *
12
*     MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY       *
13
*     CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY        *
14
*     RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY        *
15
*     DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE    *
16
*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
17
*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
18
*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A    *
19
*     PARTICULAR PURPOSE.                                                      *
20
*                                                                              *
21
*     Xilinx products are not intended for use in life support appliances,     *
22
*     devices, or systems.  Use in such applications are expressly             *
23
*     prohibited.                                                              *
24
*                                                                              *
25
*     (c) Copyright 1995-2012 Xilinx, Inc.                                     *
26
*     All rights reserved.                                                     *
27
*******************************************************************************/
28
// You must compile the wrapper file FIFORX.v when simulating
29
// the core, FIFORX. When compiling the wrapper file, be sure to
30
// reference the XilinxCoreLib Verilog simulation library. For detailed
31
// instructions, please refer to the "CORE Generator Help".
32
 
33
// The synthesis directives "translate_off/translate_on" specified below are
34
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
35
// tools. Ensure they are correct for your synthesis tool(s).
36
 
37
`timescale 1ns/1ps
38
 
39
module FIFORX(
40
  rst,
41
  wr_clk,
42
  rd_clk,
43
  din,
44
  wr_en,
45
  rd_en,
46
  dout,
47
  full,
48
  empty
49
);
50
 
51
input rst;
52
input wr_clk;
53
input rd_clk;
54
input [7 : 0] din;
55
input wr_en;
56
input rd_en;
57
output [7 : 0] dout;
58
output full;
59
output empty;
60
 
61
// synthesis translate_off
62
 
63
  FIFO_GENERATOR_V9_1 #(
64
    .C_ADD_NGC_CONSTRAINT(0),
65
    .C_APPLICATION_TYPE_AXIS(0),
66
    .C_APPLICATION_TYPE_RACH(0),
67
    .C_APPLICATION_TYPE_RDCH(0),
68
    .C_APPLICATION_TYPE_WACH(0),
69
    .C_APPLICATION_TYPE_WDCH(0),
70
    .C_APPLICATION_TYPE_WRCH(0),
71
    .C_AXI_ADDR_WIDTH(32),
72
    .C_AXI_ARUSER_WIDTH(1),
73
    .C_AXI_AWUSER_WIDTH(1),
74
    .C_AXI_BUSER_WIDTH(1),
75
    .C_AXI_DATA_WIDTH(64),
76
    .C_AXI_ID_WIDTH(4),
77
    .C_AXI_RUSER_WIDTH(1),
78
    .C_AXI_TYPE(0),
79
    .C_AXI_WUSER_WIDTH(1),
80
    .C_AXIS_TDATA_WIDTH(64),
81
    .C_AXIS_TDEST_WIDTH(4),
82
    .C_AXIS_TID_WIDTH(8),
83
    .C_AXIS_TKEEP_WIDTH(4),
84
    .C_AXIS_TSTRB_WIDTH(4),
85
    .C_AXIS_TUSER_WIDTH(4),
86
    .C_AXIS_TYPE(0),
87
    .C_COMMON_CLOCK(0),
88
    .C_COUNT_TYPE(0),
89
    .C_DATA_COUNT_WIDTH(10),
90
    .C_DEFAULT_VALUE("BlankString"),
91
    .C_DIN_WIDTH(8),
92
    .C_DIN_WIDTH_AXIS(1),
93
    .C_DIN_WIDTH_RACH(32),
94
    .C_DIN_WIDTH_RDCH(64),
95
    .C_DIN_WIDTH_WACH(32),
96
    .C_DIN_WIDTH_WDCH(64),
97
    .C_DIN_WIDTH_WRCH(2),
98
    .C_DOUT_RST_VAL("0"),
99
    .C_DOUT_WIDTH(8),
100
    .C_ENABLE_RLOCS(0),
101
    .C_ENABLE_RST_SYNC(1),
102
    .C_ERROR_INJECTION_TYPE(0),
103
    .C_ERROR_INJECTION_TYPE_AXIS(0),
104
    .C_ERROR_INJECTION_TYPE_RACH(0),
105
    .C_ERROR_INJECTION_TYPE_RDCH(0),
106
    .C_ERROR_INJECTION_TYPE_WACH(0),
107
    .C_ERROR_INJECTION_TYPE_WDCH(0),
108
    .C_ERROR_INJECTION_TYPE_WRCH(0),
109
    .C_FAMILY("spartan3"),
110
    .C_FULL_FLAGS_RST_VAL(1),
111
    .C_HAS_ALMOST_EMPTY(0),
112
    .C_HAS_ALMOST_FULL(0),
113
    .C_HAS_AXI_ARUSER(0),
114
    .C_HAS_AXI_AWUSER(0),
115
    .C_HAS_AXI_BUSER(0),
116
    .C_HAS_AXI_RD_CHANNEL(0),
117
    .C_HAS_AXI_RUSER(0),
118
    .C_HAS_AXI_WR_CHANNEL(0),
119
    .C_HAS_AXI_WUSER(0),
120
    .C_HAS_AXIS_TDATA(0),
121
    .C_HAS_AXIS_TDEST(0),
122
    .C_HAS_AXIS_TID(0),
123
    .C_HAS_AXIS_TKEEP(0),
124
    .C_HAS_AXIS_TLAST(0),
125
    .C_HAS_AXIS_TREADY(1),
126
    .C_HAS_AXIS_TSTRB(0),
127
    .C_HAS_AXIS_TUSER(0),
128
    .C_HAS_BACKUP(0),
129
    .C_HAS_DATA_COUNT(0),
130
    .C_HAS_DATA_COUNTS_AXIS(0),
131
    .C_HAS_DATA_COUNTS_RACH(0),
132
    .C_HAS_DATA_COUNTS_RDCH(0),
133
    .C_HAS_DATA_COUNTS_WACH(0),
134
    .C_HAS_DATA_COUNTS_WDCH(0),
135
    .C_HAS_DATA_COUNTS_WRCH(0),
136
    .C_HAS_INT_CLK(0),
137
    .C_HAS_MASTER_CE(0),
138
    .C_HAS_MEMINIT_FILE(0),
139
    .C_HAS_OVERFLOW(0),
140
    .C_HAS_PROG_FLAGS_AXIS(0),
141
    .C_HAS_PROG_FLAGS_RACH(0),
142
    .C_HAS_PROG_FLAGS_RDCH(0),
143
    .C_HAS_PROG_FLAGS_WACH(0),
144
    .C_HAS_PROG_FLAGS_WDCH(0),
145
    .C_HAS_PROG_FLAGS_WRCH(0),
146
    .C_HAS_RD_DATA_COUNT(0),
147
    .C_HAS_RD_RST(0),
148
    .C_HAS_RST(1),
149
    .C_HAS_SLAVE_CE(0),
150
    .C_HAS_SRST(0),
151
    .C_HAS_UNDERFLOW(0),
152
    .C_HAS_VALID(0),
153
    .C_HAS_WR_ACK(0),
154
    .C_HAS_WR_DATA_COUNT(0),
155
    .C_HAS_WR_RST(0),
156
    .C_IMPLEMENTATION_TYPE(2),
157
    .C_IMPLEMENTATION_TYPE_AXIS(1),
158
    .C_IMPLEMENTATION_TYPE_RACH(1),
159
    .C_IMPLEMENTATION_TYPE_RDCH(1),
160
    .C_IMPLEMENTATION_TYPE_WACH(1),
161
    .C_IMPLEMENTATION_TYPE_WDCH(1),
162
    .C_IMPLEMENTATION_TYPE_WRCH(1),
163
    .C_INIT_WR_PNTR_VAL(0),
164
    .C_INTERFACE_TYPE(0),
165
    .C_MEMORY_TYPE(1),
166
    .C_MIF_FILE_NAME("BlankString"),
167
    .C_MSGON_VAL(1),
168
    .C_OPTIMIZATION_MODE(0),
169
    .C_OVERFLOW_LOW(0),
170
    .C_PRELOAD_LATENCY(1),
171
    .C_PRELOAD_REGS(0),
172
    .C_PRIM_FIFO_TYPE("1kx18"),
173
    .C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
174
    .C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
175
    .C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
176
    .C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
177
    .C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
178
    .C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
179
    .C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
180
    .C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
181
    .C_PROG_EMPTY_TYPE(0),
182
    .C_PROG_EMPTY_TYPE_AXIS(0),
183
    .C_PROG_EMPTY_TYPE_RACH(0),
184
    .C_PROG_EMPTY_TYPE_RDCH(0),
185
    .C_PROG_EMPTY_TYPE_WACH(0),
186
    .C_PROG_EMPTY_TYPE_WDCH(0),
187
    .C_PROG_EMPTY_TYPE_WRCH(0),
188
    .C_PROG_FULL_THRESH_ASSERT_VAL(1021),
189
    .C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
190
    .C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
191
    .C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
192
    .C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
193
    .C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
194
    .C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
195
    .C_PROG_FULL_THRESH_NEGATE_VAL(1020),
196
    .C_PROG_FULL_TYPE(0),
197
    .C_PROG_FULL_TYPE_AXIS(0),
198
    .C_PROG_FULL_TYPE_RACH(0),
199
    .C_PROG_FULL_TYPE_RDCH(0),
200
    .C_PROG_FULL_TYPE_WACH(0),
201
    .C_PROG_FULL_TYPE_WDCH(0),
202
    .C_PROG_FULL_TYPE_WRCH(0),
203
    .C_RACH_TYPE(0),
204
    .C_RD_DATA_COUNT_WIDTH(10),
205
    .C_RD_DEPTH(1024),
206
    .C_RD_FREQ(1),
207
    .C_RD_PNTR_WIDTH(10),
208
    .C_RDCH_TYPE(0),
209
    .C_REG_SLICE_MODE_AXIS(0),
210
    .C_REG_SLICE_MODE_RACH(0),
211
    .C_REG_SLICE_MODE_RDCH(0),
212
    .C_REG_SLICE_MODE_WACH(0),
213
    .C_REG_SLICE_MODE_WDCH(0),
214
    .C_REG_SLICE_MODE_WRCH(0),
215
    .C_SYNCHRONIZER_STAGE(2),
216
    .C_UNDERFLOW_LOW(0),
217
    .C_USE_COMMON_OVERFLOW(0),
218
    .C_USE_COMMON_UNDERFLOW(0),
219
    .C_USE_DEFAULT_SETTINGS(0),
220
    .C_USE_DOUT_RST(1),
221
    .C_USE_ECC(0),
222
    .C_USE_ECC_AXIS(0),
223
    .C_USE_ECC_RACH(0),
224
    .C_USE_ECC_RDCH(0),
225
    .C_USE_ECC_WACH(0),
226
    .C_USE_ECC_WDCH(0),
227
    .C_USE_ECC_WRCH(0),
228
    .C_USE_EMBEDDED_REG(0),
229
    .C_USE_FIFO16_FLAGS(0),
230
    .C_USE_FWFT_DATA_COUNT(0),
231
    .C_VALID_LOW(0),
232
    .C_WACH_TYPE(0),
233
    .C_WDCH_TYPE(0),
234
    .C_WR_ACK_LOW(0),
235
    .C_WR_DATA_COUNT_WIDTH(10),
236
    .C_WR_DEPTH(1024),
237
    .C_WR_DEPTH_AXIS(1024),
238
    .C_WR_DEPTH_RACH(16),
239
    .C_WR_DEPTH_RDCH(1024),
240
    .C_WR_DEPTH_WACH(16),
241
    .C_WR_DEPTH_WDCH(1024),
242
    .C_WR_DEPTH_WRCH(16),
243
    .C_WR_FREQ(1),
244
    .C_WR_PNTR_WIDTH(10),
245
    .C_WR_PNTR_WIDTH_AXIS(10),
246
    .C_WR_PNTR_WIDTH_RACH(4),
247
    .C_WR_PNTR_WIDTH_RDCH(10),
248
    .C_WR_PNTR_WIDTH_WACH(4),
249
    .C_WR_PNTR_WIDTH_WDCH(10),
250
    .C_WR_PNTR_WIDTH_WRCH(4),
251
    .C_WR_RESPONSE_LATENCY(1),
252
    .C_WRCH_TYPE(0)
253
  )
254
  inst (
255
    .RST(rst),
256
    .WR_CLK(wr_clk),
257
    .RD_CLK(rd_clk),
258
    .DIN(din),
259
    .WR_EN(wr_en),
260
    .RD_EN(rd_en),
261
    .DOUT(dout),
262
    .FULL(full),
263
    .EMPTY(empty),
264
    .BACKUP(),
265
    .BACKUP_MARKER(),
266
    .CLK(),
267
    .SRST(),
268
    .WR_RST(),
269
    .RD_RST(),
270
    .PROG_EMPTY_THRESH(),
271
    .PROG_EMPTY_THRESH_ASSERT(),
272
    .PROG_EMPTY_THRESH_NEGATE(),
273
    .PROG_FULL_THRESH(),
274
    .PROG_FULL_THRESH_ASSERT(),
275
    .PROG_FULL_THRESH_NEGATE(),
276
    .INT_CLK(),
277
    .INJECTDBITERR(),
278
    .INJECTSBITERR(),
279
    .ALMOST_FULL(),
280
    .WR_ACK(),
281
    .OVERFLOW(),
282
    .ALMOST_EMPTY(),
283
    .VALID(),
284
    .UNDERFLOW(),
285
    .DATA_COUNT(),
286
    .RD_DATA_COUNT(),
287
    .WR_DATA_COUNT(),
288
    .PROG_FULL(),
289
    .PROG_EMPTY(),
290
    .SBITERR(),
291
    .DBITERR(),
292
    .M_ACLK(),
293
    .S_ACLK(),
294
    .S_ARESETN(),
295
    .M_ACLK_EN(),
296
    .S_ACLK_EN(),
297
    .S_AXI_AWID(),
298
    .S_AXI_AWADDR(),
299
    .S_AXI_AWLEN(),
300
    .S_AXI_AWSIZE(),
301
    .S_AXI_AWBURST(),
302
    .S_AXI_AWLOCK(),
303
    .S_AXI_AWCACHE(),
304
    .S_AXI_AWPROT(),
305
    .S_AXI_AWQOS(),
306
    .S_AXI_AWREGION(),
307
    .S_AXI_AWUSER(),
308
    .S_AXI_AWVALID(),
309
    .S_AXI_AWREADY(),
310
    .S_AXI_WID(),
311
    .S_AXI_WDATA(),
312
    .S_AXI_WSTRB(),
313
    .S_AXI_WLAST(),
314
    .S_AXI_WUSER(),
315
    .S_AXI_WVALID(),
316
    .S_AXI_WREADY(),
317
    .S_AXI_BID(),
318
    .S_AXI_BRESP(),
319
    .S_AXI_BUSER(),
320
    .S_AXI_BVALID(),
321
    .S_AXI_BREADY(),
322
    .M_AXI_AWID(),
323
    .M_AXI_AWADDR(),
324
    .M_AXI_AWLEN(),
325
    .M_AXI_AWSIZE(),
326
    .M_AXI_AWBURST(),
327
    .M_AXI_AWLOCK(),
328
    .M_AXI_AWCACHE(),
329
    .M_AXI_AWPROT(),
330
    .M_AXI_AWQOS(),
331
    .M_AXI_AWREGION(),
332
    .M_AXI_AWUSER(),
333
    .M_AXI_AWVALID(),
334
    .M_AXI_AWREADY(),
335
    .M_AXI_WID(),
336
    .M_AXI_WDATA(),
337
    .M_AXI_WSTRB(),
338
    .M_AXI_WLAST(),
339
    .M_AXI_WUSER(),
340
    .M_AXI_WVALID(),
341
    .M_AXI_WREADY(),
342
    .M_AXI_BID(),
343
    .M_AXI_BRESP(),
344
    .M_AXI_BUSER(),
345
    .M_AXI_BVALID(),
346
    .M_AXI_BREADY(),
347
    .S_AXI_ARID(),
348
    .S_AXI_ARADDR(),
349
    .S_AXI_ARLEN(),
350
    .S_AXI_ARSIZE(),
351
    .S_AXI_ARBURST(),
352
    .S_AXI_ARLOCK(),
353
    .S_AXI_ARCACHE(),
354
    .S_AXI_ARPROT(),
355
    .S_AXI_ARQOS(),
356
    .S_AXI_ARREGION(),
357
    .S_AXI_ARUSER(),
358
    .S_AXI_ARVALID(),
359
    .S_AXI_ARREADY(),
360
    .S_AXI_RID(),
361
    .S_AXI_RDATA(),
362
    .S_AXI_RRESP(),
363
    .S_AXI_RLAST(),
364
    .S_AXI_RUSER(),
365
    .S_AXI_RVALID(),
366
    .S_AXI_RREADY(),
367
    .M_AXI_ARID(),
368
    .M_AXI_ARADDR(),
369
    .M_AXI_ARLEN(),
370
    .M_AXI_ARSIZE(),
371
    .M_AXI_ARBURST(),
372
    .M_AXI_ARLOCK(),
373
    .M_AXI_ARCACHE(),
374
    .M_AXI_ARPROT(),
375
    .M_AXI_ARQOS(),
376
    .M_AXI_ARREGION(),
377
    .M_AXI_ARUSER(),
378
    .M_AXI_ARVALID(),
379
    .M_AXI_ARREADY(),
380
    .M_AXI_RID(),
381
    .M_AXI_RDATA(),
382
    .M_AXI_RRESP(),
383
    .M_AXI_RLAST(),
384
    .M_AXI_RUSER(),
385
    .M_AXI_RVALID(),
386
    .M_AXI_RREADY(),
387
    .S_AXIS_TVALID(),
388
    .S_AXIS_TREADY(),
389
    .S_AXIS_TDATA(),
390
    .S_AXIS_TSTRB(),
391
    .S_AXIS_TKEEP(),
392
    .S_AXIS_TLAST(),
393
    .S_AXIS_TID(),
394
    .S_AXIS_TDEST(),
395
    .S_AXIS_TUSER(),
396
    .M_AXIS_TVALID(),
397
    .M_AXIS_TREADY(),
398
    .M_AXIS_TDATA(),
399
    .M_AXIS_TSTRB(),
400
    .M_AXIS_TKEEP(),
401
    .M_AXIS_TLAST(),
402
    .M_AXIS_TID(),
403
    .M_AXIS_TDEST(),
404
    .M_AXIS_TUSER(),
405
    .AXI_AW_INJECTSBITERR(),
406
    .AXI_AW_INJECTDBITERR(),
407
    .AXI_AW_PROG_FULL_THRESH(),
408
    .AXI_AW_PROG_EMPTY_THRESH(),
409
    .AXI_AW_DATA_COUNT(),
410
    .AXI_AW_WR_DATA_COUNT(),
411
    .AXI_AW_RD_DATA_COUNT(),
412
    .AXI_AW_SBITERR(),
413
    .AXI_AW_DBITERR(),
414
    .AXI_AW_OVERFLOW(),
415
    .AXI_AW_UNDERFLOW(),
416
    .AXI_AW_PROG_FULL(),
417
    .AXI_AW_PROG_EMPTY(),
418
    .AXI_W_INJECTSBITERR(),
419
    .AXI_W_INJECTDBITERR(),
420
    .AXI_W_PROG_FULL_THRESH(),
421
    .AXI_W_PROG_EMPTY_THRESH(),
422
    .AXI_W_DATA_COUNT(),
423
    .AXI_W_WR_DATA_COUNT(),
424
    .AXI_W_RD_DATA_COUNT(),
425
    .AXI_W_SBITERR(),
426
    .AXI_W_DBITERR(),
427
    .AXI_W_OVERFLOW(),
428
    .AXI_W_UNDERFLOW(),
429
    .AXI_B_INJECTSBITERR(),
430
    .AXI_W_PROG_FULL(),
431
    .AXI_W_PROG_EMPTY(),
432
    .AXI_B_INJECTDBITERR(),
433
    .AXI_B_PROG_FULL_THRESH(),
434
    .AXI_B_PROG_EMPTY_THRESH(),
435
    .AXI_B_DATA_COUNT(),
436
    .AXI_B_WR_DATA_COUNT(),
437
    .AXI_B_RD_DATA_COUNT(),
438
    .AXI_B_SBITERR(),
439
    .AXI_B_DBITERR(),
440
    .AXI_B_OVERFLOW(),
441
    .AXI_B_UNDERFLOW(),
442
    .AXI_AR_INJECTSBITERR(),
443
    .AXI_B_PROG_FULL(),
444
    .AXI_B_PROG_EMPTY(),
445
    .AXI_AR_INJECTDBITERR(),
446
    .AXI_AR_PROG_FULL_THRESH(),
447
    .AXI_AR_PROG_EMPTY_THRESH(),
448
    .AXI_AR_DATA_COUNT(),
449
    .AXI_AR_WR_DATA_COUNT(),
450
    .AXI_AR_RD_DATA_COUNT(),
451
    .AXI_AR_SBITERR(),
452
    .AXI_AR_DBITERR(),
453
    .AXI_AR_OVERFLOW(),
454
    .AXI_AR_UNDERFLOW(),
455
    .AXI_AR_PROG_FULL(),
456
    .AXI_AR_PROG_EMPTY(),
457
    .AXI_R_INJECTSBITERR(),
458
    .AXI_R_INJECTDBITERR(),
459
    .AXI_R_PROG_FULL_THRESH(),
460
    .AXI_R_PROG_EMPTY_THRESH(),
461
    .AXI_R_DATA_COUNT(),
462
    .AXI_R_WR_DATA_COUNT(),
463
    .AXI_R_RD_DATA_COUNT(),
464
    .AXI_R_SBITERR(),
465
    .AXI_R_DBITERR(),
466
    .AXI_R_OVERFLOW(),
467
    .AXI_R_UNDERFLOW(),
468
    .AXIS_INJECTSBITERR(),
469
    .AXI_R_PROG_FULL(),
470
    .AXI_R_PROG_EMPTY(),
471
    .AXIS_INJECTDBITERR(),
472
    .AXIS_PROG_FULL_THRESH(),
473
    .AXIS_PROG_EMPTY_THRESH(),
474
    .AXIS_DATA_COUNT(),
475
    .AXIS_WR_DATA_COUNT(),
476
    .AXIS_RD_DATA_COUNT(),
477
    .AXIS_SBITERR(),
478
    .AXIS_DBITERR(),
479
    .AXIS_OVERFLOW(),
480
    .AXIS_UNDERFLOW(),
481
    .AXIS_PROG_FULL(),
482
    .AXIS_PROG_EMPTY()
483
  );
484
 
485
// synthesis translate_on
486
 
487
endmodule

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