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[/] [complex-gaussian-pseudo-random-number-generator/] [trunk/] [urng/] [MT_SET.vhd] - Blame information for rev 2

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--/////////////////////////MT BLOCK///////////////////////////////
--Purpose: to produce functionality equivalent to following C code
--         excluding a momry module
--                      void mt_set (void *vstate, unsigned long int s)
--                      {
--                              mt_state_t *state = (mt_state_t *) vstate;
--                              int i;
--                              if (s == 0)
--                              s = 4357;       /* the default seed is 4357 */
--      #define LCG(x) ((69069 * x) + 1) &0xffffffffUL
--                              for (i = 0; i < N; i++)
--                              {
--                                      state->mt[i] = s & 0xffff0000UL;
--                                      s = LCG(s);
--                                      state->mt[i] |= (s &0xffff0000UL) >> 16;
--                                      s = LCG(s);
--                              }
--                              state->mti = i;
--                      }
--Created by: Minzhen Ren
--Last Modified by: Minzhen Ren
--Last Modified Date: Auguest 28, 2010
--Lately Updates: 
--/////////////////////////////////////////////////////////////////
library ieee;
        use ieee.std_logic_1164.all;
        use ieee.std_logic_unsigned.all;
        use ieee.numeric_std.all;
        use ieee.math_real.all;
 
entity MT_SET is
        generic(
                DATA_WIDTH : Natural := 32
        );
        port(
                signal CLK      : in  std_logic;
                signal RESET    : in  std_logic;
                signal IDLE_SIG : in  std_logic;
                signal S_IN     : in  std_logic_vector( DATA_WIDTH-1 downto 0 );
                signal S_OUT    : out std_logic_vector( DATA_WIDTH-1 downto 0 )
        );
end MT_SET;
 
architecture BEHAV of MT_SET is
 
        --state machine
        type STATE_TYPE is (INITIAL, RUNNING, IDLE);
        signal CS : STATE_TYPE;
        signal NS : STATE_TYPE;
        signal INNER_STATE  : std_logic_vector(2 downto 0);
 
        signal MASK             : std_logic_vector( DATA_WIDTH-1 downto 0 );
        signal S_D              : std_logic_vector( DATA_WIDTH-1 downto 0 );
        signal S_Q              : std_logic_vector( DATA_WIDTH-1 downto 0 );
        signal IDLE_IN      : std_logic;
 
        signal S_LCG1   : std_logic_vector( DATA_WIDTH-1 downto 0 );
        signal S_LCG1_Q : std_logic_vector( DATA_WIDTH-1 downto 0 );
        signal S_LCG2   : std_logic_vector( DATA_WIDTH-1 downto 0 );
 
        signal S_OP1_D  : std_logic_vector( DATA_WIDTH-1 downto 0 );
        signal S_OP1_Q  : std_logic_vector( DATA_WIDTH-1 downto 0 );
        signal S_OP2    : std_logic_vector( DATA_WIDTH-1 downto 0 );
 
        component REG is
                generic(
                        BIT_WIDTH : Natural := 32
                );
                port(
                        CLK       : in  std_logic;
                        RESET     : in  std_logic; -- high asserted
                        DATA_IN   : in  std_logic_vector( BIT_WIDTH-1 downto 0 );
                        DATA_OUT  : out std_logic_vector( BIT_WIDTH-1 downto 0 )
                );
        end component;
 
        component LCG is
                generic(
                        DATA_WIDTH : Natural := 32
                );
                port(
                        CLK   : in  std_logic;
                        RESET : in  std_logic;
                        X_IN  : in  std_logic_vector( DATA_WIDTH-1 downto 0 );
                        X_OUT : out std_logic_vector( DATA_WIDTH-1 downto 0 )
                );
        end component;
 
        begin
 
        MASK <= "11111111111111110000000000000000"; --0xffffffffUL
        IDLE_IN <= IDLE_SIG;
 
        CURRENT_STATE : process(CLK, RESET)
        begin
                if RESET = '1' then
                        CS <=INITIAL;
                elsif CLK='1' and CLK'event then
                        CS <= NS;
                end if;
        end process;
 
        NEXT_STATE : process(CS, IDLE_IN)
        begin
                if CS = INITIAL then
                        NS <= RUNNING;
                elsif CS = RUNNING then
                        if IDLE_IN = '1' then
                                NS <= IDLE;
                        else
                                NS <= CS;
                        end if;
                elsif CS = IDLE then
                        if IDLE_IN = '0' then
                                NS <= RUNNING;
                        else
                                NS <= CS;
                        end if;
                else
                        NS <= CS;
                end if;
 
        end process;
 
        INNER_STATE_PROCESS : process(RESET, CLK)
        begin
                if RESET = '1' then
                        INNER_STATE <= (others => '0');
                elsif CLK'event and CLK='1' then
                        if INNER_STATE(2) = '0' then
                                INNER_STATE <= INNER_STATE + 1;
                        else
                                INNER_STATE <= "001";
                        end if;
                end if;
        end process;
 
        --input mux
        S_D <=  S_IN when CS = INITIAL else
                        S_Q when CS = IDLE else
                        S_LCG2 when INNER_STATE(2) = '1' else
                        S_Q;
 
        S_IN_REG : REG
        port map(
                CLK => CLK,
                RESET => RESET,
                DATA_IN => S_D,
                DATA_OUT => S_Q
        );
 
        S_OP1_D <= S_Q and MASK;
 
        S_OP1_REG : REG
    port map(
                CLK => CLK,
                RESET => RESET,
                DATA_IN => S_OP1_D,
                DATA_OUT => S_OP1_Q
        );
 
        LCG1 : LCG
        port map(
                CLK => CLK,
                RESET => RESET,
                X_IN => S_Q,
                X_OUT => S_LCG1
        );
 
        S_OP2 <= S_LCG1 and MASK;
        S_OUT <= S_OP1_Q or ("0000000000000000" & S_OP2(31 downto 16));
 
        S_LCG1_REG : REG
    port map(
                CLK => CLK,
                RESET => RESET,
                DATA_IN => S_LCG1,
                DATA_OUT => S_LCG1_Q
        );
 
        LCG2 : LCG
        port map(
                CLK => CLK,
                RESET => RESET,
                X_IN => S_LCG1_Q,
                X_OUT => S_LCG2
        );
 
        -- S_OUT_REG1 : REG
    -- port map(
                -- CLK => CLK,
                -- RESET => RESET,
                -- DATA_IN => S_OUT_D,
                -- DATA_OUT => S_OUT_DD
    -- );
 
        -- S_OUT_REG2 : REG
    -- port map(
                -- CLK => CLK,
                -- RESET => RESET,
                -- DATA_IN => S_OUT_DD,
                -- DATA_OUT => S_OUT
    -- );
end BEHAV;

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Subversion Repositories complex-gaussian-pseudo-random-number-generator

[/] [complex-gaussian-pseudo-random-number-generator/] [trunk/] [urng/] [MT_SET.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	cowboyor	`--/////////////////////////MT BLOCK///////////////////////////////`
2			`--Purpose: to produce functionality equivalent to following C code`
3			`-- excluding a momry module`
4			`-- void mt_set (void *vstate, unsigned long int s)`
5			`-- {`
6			`-- mt_state_t state = (mt_state_t ) vstate;`
7			`-- int i;`
8			`-- if (s == 0)`
9			`-- s = 4357; /* the default seed is 4357 */`
10			`-- #define LCG(x) ((69069 * x) + 1) &0xffffffffUL`
11			`-- for (i = 0; i < N; i++)`
12			`-- {`
13			`-- state->mt[i] = s & 0xffff0000UL;`
14			`-- s = LCG(s);`
15			`-- state->mt[i] \|= (s &0xffff0000UL) >> 16;`
16			`-- s = LCG(s);`
17			`-- }`
18			`-- state->mti = i;`
19			`-- }`
20			`--Created by: Minzhen Ren`
21			`--Last Modified by: Minzhen Ren`
22			`--Last Modified Date: Auguest 28, 2010`
23			`--Lately Updates:`
24			`--/////////////////////////////////////////////////////////////////`
25			`library ieee;`
26			`use ieee.std_logic_1164.all;`
27			`use ieee.std_logic_unsigned.all;`
28			`use ieee.numeric_std.all;`
29			`use ieee.math_real.all;`
30
31			`entity MT_SET is`
32			`generic(`
33			`DATA_WIDTH : Natural := 32`
34			`);`
35			`port(`
36			`signal CLK : in std_logic;`
37			`signal RESET : in std_logic;`
38			`signal IDLE_SIG : in std_logic;`
39			`signal S_IN : in std_logic_vector( DATA_WIDTH-1 downto 0 );`
40			`signal S_OUT : out std_logic_vector( DATA_WIDTH-1 downto 0 )`
41			`);`
42			`end MT_SET;`
43
44			`architecture BEHAV of MT_SET is`
45
46			`--state machine`
47			`type STATE_TYPE is (INITIAL, RUNNING, IDLE);`
48			`signal CS : STATE_TYPE;`
49			`signal NS : STATE_TYPE;`
50			`signal INNER_STATE : std_logic_vector(2 downto 0);`
51
52			`signal MASK : std_logic_vector( DATA_WIDTH-1 downto 0 );`
53			`signal S_D : std_logic_vector( DATA_WIDTH-1 downto 0 );`
54			`signal S_Q : std_logic_vector( DATA_WIDTH-1 downto 0 );`
55			`signal IDLE_IN : std_logic;`
56
57			`signal S_LCG1 : std_logic_vector( DATA_WIDTH-1 downto 0 );`
58			`signal S_LCG1_Q : std_logic_vector( DATA_WIDTH-1 downto 0 );`
59			`signal S_LCG2 : std_logic_vector( DATA_WIDTH-1 downto 0 );`
60
61			`signal S_OP1_D : std_logic_vector( DATA_WIDTH-1 downto 0 );`
62			`signal S_OP1_Q : std_logic_vector( DATA_WIDTH-1 downto 0 );`
63			`signal S_OP2 : std_logic_vector( DATA_WIDTH-1 downto 0 );`
64
65			`component REG is`
66			`generic(`
67			`BIT_WIDTH : Natural := 32`
68			`);`
69			`port(`
70			`CLK : in std_logic;`
71			`RESET : in std_logic; -- high asserted`
72			`DATA_IN : in std_logic_vector( BIT_WIDTH-1 downto 0 );`
73			`DATA_OUT : out std_logic_vector( BIT_WIDTH-1 downto 0 )`
74			`);`
75			`end component;`
76
77			`component LCG is`
78			`generic(`
79			`DATA_WIDTH : Natural := 32`
80			`);`
81			`port(`
82			`CLK : in std_logic;`
83			`RESET : in std_logic;`
84			`X_IN : in std_logic_vector( DATA_WIDTH-1 downto 0 );`
85			`X_OUT : out std_logic_vector( DATA_WIDTH-1 downto 0 )`
86			`);`
87			`end component;`
88
89			`begin`
90
91			`MASK <= "11111111111111110000000000000000"; --0xffffffffUL`
92			`IDLE_IN <= IDLE_SIG;`
93
94			`CURRENT_STATE : process(CLK, RESET)`
95			`begin`
96			`if RESET = '1' then`
97			`CS <=INITIAL;`
98			`elsif CLK='1' and CLK'event then`
99			`CS <= NS;`
100			`end if;`
101			`end process;`
102
103			`NEXT_STATE : process(CS, IDLE_IN)`
104			`begin`
105			`if CS = INITIAL then`
106			`NS <= RUNNING;`
107			`elsif CS = RUNNING then`
108			`if IDLE_IN = '1' then`
109			`NS <= IDLE;`
110			`else`
111			`NS <= CS;`
112			`end if;`
113			`elsif CS = IDLE then`
114			`if IDLE_IN = '0' then`
115			`NS <= RUNNING;`
116			`else`
117			`NS <= CS;`
118			`end if;`
119			`else`
120			`NS <= CS;`
121			`end if;`
122
123			`end process;`
124
125			`INNER_STATE_PROCESS : process(RESET, CLK)`
126			`begin`
127			`if RESET = '1' then`
128			`INNER_STATE <= (others => '0');`
129			`elsif CLK'event and CLK='1' then`
130			`if INNER_STATE(2) = '0' then`
131			`INNER_STATE <= INNER_STATE + 1;`
132			`else`
133			`INNER_STATE <= "001";`
134			`end if;`
135			`end if;`
136			`end process;`
137
138			`--input mux`
139			`S_D <= S_IN when CS = INITIAL else`
140			`S_Q when CS = IDLE else`
141			`S_LCG2 when INNER_STATE(2) = '1' else`
142			`S_Q;`
143
144			`S_IN_REG : REG`
145			`port map(`
146			`CLK => CLK,`
147			`RESET => RESET,`
148			`DATA_IN => S_D,`
149			`DATA_OUT => S_Q`
150			`);`
151
152			`S_OP1_D <= S_Q and MASK;`
153
154			`S_OP1_REG : REG`
155			`port map(`
156			`CLK => CLK,`
157			`RESET => RESET,`
158			`DATA_IN => S_OP1_D,`
159			`DATA_OUT => S_OP1_Q`
160			`);`
161
162			`LCG1 : LCG`
163			`port map(`
164			`CLK => CLK,`
165			`RESET => RESET,`
166			`X_IN => S_Q,`
167			`X_OUT => S_LCG1`
168			`);`
169
170			`S_OP2 <= S_LCG1 and MASK;`
171			`S_OUT <= S_OP1_Q or ("0000000000000000" & S_OP2(31 downto 16));`
172
173			`S_LCG1_REG : REG`
174			`port map(`
175			`CLK => CLK,`
176			`RESET => RESET,`
177			`DATA_IN => S_LCG1,`
178			`DATA_OUT => S_LCG1_Q`
179			`);`
180
181			`LCG2 : LCG`
182			`port map(`
183			`CLK => CLK,`
184			`RESET => RESET,`
185			`X_IN => S_LCG1_Q,`
186			`X_OUT => S_LCG2`
187			`);`
188
189			`-- S_OUT_REG1 : REG`
190			`-- port map(`
191			`-- CLK => CLK,`
192			`-- RESET => RESET,`
193			`-- DATA_IN => S_OUT_D,`
194			`-- DATA_OUT => S_OUT_DD`
195			`-- );`
196
197			`-- S_OUT_REG2 : REG`
198			`-- port map(`
199			`-- CLK => CLK,`
200			`-- RESET => RESET,`
201			`-- DATA_IN => S_OUT_DD,`
202			`-- DATA_OUT => S_OUT`
203			`-- );`
204			`end BEHAV;`