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[/] [copyblaze/] [trunk/] [copyblaze/] [rtl/] [vhdl/] [ip/] [wb_3p_spram_wrapper/] [tb_wb_Np_ram.vhd] - Blame information for rev 65

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----------------------------------------------------------------------------------
-- Company:       VISENGI S.L. (www.visengi.com)
-- Engineer:      Victor Lopez Lorenzo (victor.lopez (at) visengi (dot) com)
-- 
-- Create Date:    23:44:13 22/August/2008 
-- Project Name:   Triple Port WISHBONE SPRAM Wrapper
-- Tool versions:  Xilinx ISE 9.2i
-- Description: 
--
-- Description: This is a wrapper for an inferred single port RAM, that converts it
--              into a Three-port RAM with one WISHBONE slave interface for each port. 
--
--
-- LICENSE TERMS: GNU LESSER GENERAL PUBLIC LICENSE Version 2.1
--     That is you may use it in ANY project (commercial or not) without paying a cent.
--     You are only required to include in the copyrights/about section of accompanying 
--     software and manuals of use that your system contains a "3P WB SPRAM Wrapper
--     (C) VISENGI S.L. under LGPL license"
--     This holds also in the case where you modify the core, as the resulting core
--     would be a derived work.
--     Also, we would like to know if you use this core in a project of yours, just an email will do.
--
--    Please take good note of the disclaimer section of the LPGL license, as we don't
--    take any responsability for anything that this core does.
----------------------------------------------------------------------------------
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY tb_wb_Np_ram_vhd IS
END tb_wb_Np_ram_vhd;
 
ARCHITECTURE behavior OF tb_wb_Np_ram_vhd IS
 
        -- Component Declaration for the Unit Under Test (UUT)
        COMPONENT wb_Np_ram
        PORT(
                wb_clk_i : IN std_logic;
                wb_rst_i : IN std_logic;
                wb1_cyc_i : IN std_logic;
                wb1_stb_i : IN std_logic;
                wb1_we_i : IN std_logic;
                wb1_adr_i : IN std_logic_vector(7 downto 0);
                wb1_dat_i : IN std_logic_vector(31 downto 0);
                wb2_cyc_i : IN std_logic;
                wb2_stb_i : IN std_logic;
                wb2_we_i : IN std_logic;
                wb2_adr_i : IN std_logic_vector(7 downto 0);
                wb2_dat_i : IN std_logic_vector(31 downto 0);
                wb3_cyc_i : IN std_logic;
                wb3_stb_i : IN std_logic;
                wb3_we_i : IN std_logic;
                wb3_adr_i : IN std_logic_vector(7 downto 0);
                wb3_dat_i : IN std_logic_vector(31 downto 0);
                wb1_dat_o : OUT std_logic_vector(31 downto 0);
                wb1_ack_o : OUT std_logic;
                wb2_dat_o : OUT std_logic_vector(31 downto 0);
                wb2_ack_o : OUT std_logic;
                wb3_dat_o : OUT std_logic_vector(31 downto 0);
                wb3_ack_o : OUT std_logic
                );
        END COMPONENT;
 
        --Inputs
        SIGNAL wb_clk_i :  std_logic := '0';
        SIGNAL wb_rst_i :  std_logic := '0';
        SIGNAL wb1_cyc_i :  std_logic := '0';
        SIGNAL wb1_stb_i :  std_logic := '0';
        SIGNAL wb1_we_i :  std_logic := '0';
        SIGNAL wb2_cyc_i :  std_logic := '0';
        SIGNAL wb2_stb_i :  std_logic := '0';
        SIGNAL wb2_we_i :  std_logic := '0';
        SIGNAL wb3_cyc_i :  std_logic := '0';
        SIGNAL wb3_stb_i :  std_logic := '0';
        SIGNAL wb3_we_i :  std_logic := '0';
        SIGNAL wb1_adr_i :  std_logic_vector(7 downto 0) := (others=>'0');
        SIGNAL wb1_dat_i :  std_logic_vector(31 downto 0) := (others=>'0');
        SIGNAL wb2_adr_i :  std_logic_vector(7 downto 0) := (others=>'0');
        SIGNAL wb2_dat_i :  std_logic_vector(31 downto 0) := (others=>'0');
        SIGNAL wb3_adr_i :  std_logic_vector(7 downto 0) := (others=>'0');
        SIGNAL wb3_dat_i :  std_logic_vector(31 downto 0) := (others=>'0');
 
        --Outputs
        SIGNAL wb1_dat_o :  std_logic_vector(31 downto 0);
        SIGNAL wb1_ack_o :  std_logic;
        SIGNAL wb2_dat_o :  std_logic_vector(31 downto 0);
        SIGNAL wb2_ack_o :  std_logic;
        SIGNAL wb3_dat_o :  std_logic_vector(31 downto 0);
        SIGNAL wb3_ack_o :  std_logic;
 
BEGIN
 
        -- Instantiate the Unit Under Test (UUT)
        uut: wb_Np_ram PORT MAP(
                wb_clk_i => wb_clk_i,
                wb_rst_i => wb_rst_i,
                wb1_cyc_i => wb1_cyc_i,
                wb1_stb_i => wb1_stb_i,
                wb1_we_i => wb1_we_i,
                wb1_adr_i => wb1_adr_i,
                wb1_dat_i => wb1_dat_i,
                wb1_dat_o => wb1_dat_o,
                wb1_ack_o => wb1_ack_o,
                wb2_cyc_i => wb2_cyc_i,
                wb2_stb_i => wb2_stb_i,
                wb2_we_i => wb2_we_i,
                wb2_adr_i => wb2_adr_i,
                wb2_dat_i => wb2_dat_i,
                wb2_dat_o => wb2_dat_o,
                wb2_ack_o => wb2_ack_o,
                wb3_cyc_i => wb3_cyc_i,
                wb3_stb_i => wb3_stb_i,
                wb3_we_i => wb3_we_i,
                wb3_adr_i => wb3_adr_i,
                wb3_dat_i => wb3_dat_i,
                wb3_dat_o => wb3_dat_o,
                wb3_ack_o => wb3_ack_o
        );
 
 
 
 
 
 
   wb1_control : process (wb_rst_i, wb_clk_i)
      variable WaitACKWB : std_logic;
      variable data : std_logic_vector(31 downto 0);
      variable State : integer;
   begin
      if (wb_rst_i = '1') then
         wb1_dat_i <= (others => '0');
         wb1_adr_i <= (others => '0');
         wb1_we_i <= '0';
         wb1_stb_i <= '0';
         wb1_cyc_i <= '0';
 
         data := (others => '0');
         WaitACKWB := '0';
         State := 0;
      elsif (wb_clk_i = '1' and wb_clk_i'event) then
         if (WaitACKWB = '1') then
            if (wb1_ack_o = '1') then
               WaitACKWB := '0';
               wb1_we_i <= '0';
               wb1_stb_i <= '0';
               wb1_cyc_i <= '0';
               data := wb1_dat_o;
            end if;
         end if;
 
         if (WaitACKWB = '0') then
            case State is
               when 0 => --init
                                                wb1_adr_i <= X"00";
                                                wb1_dat_i <= x"00000001";
                                                wb1_we_i <= '1';
                  WaitACKWB := '1';
                  State := State + 1;
               when 1 =>
                                                wb1_adr_i <= X"01";
                                                wb1_dat_i <= x"00000002";
                                                wb1_we_i <= '1';
                  WaitACKWB := '1';
                  State := State + 1;
               when 2 =>
                  wb1_adr_i <= X"02";
                                                wb1_dat_i <= x"00000003";
                                                wb1_we_i <= '1';
                  WaitACKWB := '1';
                  State := State + 1;
               when 3 =>
                  State := State + 1;
               when 4 =>
                  wb1_adr_i <= X"00";
                                                wb1_we_i <= '0';
                  WaitACKWB := '1';
                  State := State + 1;
               when 5 =>
                  State := State + 1;
               when 6 =>
                  State := State + 1;
               when 7 =>
                  wb1_adr_i <= X"01";
                  wb1_dat_i <= data;
                                                wb1_we_i <= '1';
                  WaitACKWB := '1';
                  State := State + 1;
               when 8 =>
                  wb1_adr_i <= X"05";
                  wb1_dat_i <= x"00500FA0";
                                                wb1_we_i <= '1';
                  WaitACKWB := '1';
                  State := 0;
               when 45 =>
                  report "-----------> Testbench Finished OK!" severity FAILURE; --everything went fine, it's just to stop the simulation
 
               when others =>
                  null;
            end case;
 
            if (WaitACKWB = '1') then
               wb1_stb_i <= '1';
               wb1_cyc_i <= '1';
            end if;
         end if;
      end if;
   end process wb1_control;
 
 
 
 
 
   wb2_control : process (wb_rst_i, wb_clk_i)
      variable WaitACKWB : std_logic;
      variable data : std_logic_vector(31 downto 0);
      variable State : integer;
   begin
      if (wb_rst_i = '1') then
         wb2_dat_i <= (others => '0');
         wb2_adr_i <= (others => '0');
         wb2_we_i <= '0';
         wb2_stb_i <= '0';
         wb2_cyc_i <= '0';
 
         data := (others => '0');
         WaitACKWB := '0';
         State := 0;
      elsif (wb_clk_i = '1' and wb_clk_i'event) then
         if (WaitACKWB = '1') then
            if (wb2_ack_o = '1') then
               WaitACKWB := '0';
               wb2_we_i <= '0';
               wb2_stb_i <= '0';
               wb2_cyc_i <= '0';
               data := wb2_dat_o;
            end if;
         end if;
 
         if (WaitACKWB = '0') then
            case State is
               when 0 => --init
                                                wb2_adr_i <= X"05";
                                                wb2_we_i <= '0';
                  WaitACKWB := '1';
                  State := State + 1;
               when 1 =>
                  State := State + 1;
               when 2 =>
                  State := State + 1;
               when 3 =>
                  State := State + 1;
               when 4 =>
                                                wb2_adr_i <= X"04";
                                                wb2_dat_i <= x"00000002";
                                                wb2_we_i <= '1';
                  WaitACKWB := '1';
                  State := State + 1;
               when 5 =>
                  State := State + 1;
               when 6 =>
                  State := State + 1;
               when 7 =>
                  State := State + 1;
               when 8 =>
                  wb2_adr_i <= X"03";
                                                wb2_we_i <= '0';
                  WaitACKWB := '1';
                  State := State + 1;
               when 9 =>
                  State := State + 1;
               when 10 =>
                  wb2_adr_i <= X"02";
                                                wb2_we_i <= '0';
                  WaitACKWB := '1';
                  State := State + 1;
               when 11 =>
                  State := State + 1;
               when 12 =>
                  State := State + 1;
               when 13 =>
                  State := State + 1;
               when 14 =>
                  wb2_adr_i <= X"01";
                                                wb2_we_i <= '0';
                  WaitACKWB := '1';
                  State := State + 1;
               when 15 =>
                  State := State + 1;
               when 16 =>
                  State := State + 1;
               when 17 =>
                  wb2_adr_i <= X"05";
                  wb2_dat_i <= data;
                                                wb2_we_i <= '1';
                  WaitACKWB := '1';
                  State := 0;
               when others =>
                  null;
            end case;
 
            if (WaitACKWB = '1') then
               wb2_stb_i <= '1';
               wb2_cyc_i <= '1';
            end if;
         end if;
      end if;
   end process wb2_control;
 
 
 
   wb3_control : process (wb_rst_i, wb_clk_i)
      variable WaitACKWB : std_logic;
      variable data : std_logic_vector(31 downto 0);
      variable State : integer;
   begin
      if (wb_rst_i = '1') then
         wb3_dat_i <= (others => '0');
         wb3_adr_i <= (others => '0');
         wb3_we_i <= '0';
         wb3_stb_i <= '0';
         wb3_cyc_i <= '0';
 
         data := (others => '0');
         WaitACKWB := '0';
         State := 0;
      elsif (wb_clk_i = '1' and wb_clk_i'event) then
         if (WaitACKWB = '1') then
            if (wb3_ack_o = '1') then
               WaitACKWB := '0';
               wb3_we_i <= '0';
               wb3_stb_i <= '0';
               wb3_cyc_i <= '0';
               data := wb3_dat_o;
            end if;
         end if;
 
         if (WaitACKWB = '0') then
            case State is
               when 0 =>
                  State := State + 1;
               when 1 => --init
                                                wb3_adr_i <= X"05";
                                                wb3_we_i <= '0';
                  WaitACKWB := '1';
                  State := State + 1;
               when 2 =>
                                                wb3_adr_i <= X"02";
                                                wb3_dat_i <= x"00000002";
                                                wb3_we_i <= '1';
                  WaitACKWB := '1';
                  State := State + 1;
               when 3 =>
                  State := State + 1;
               when 4 =>
                  wb3_adr_i <= X"01";
                                                wb3_dat_i <= x"00000003";
                                                wb3_we_i <= '1';
                  WaitACKWB := '1';
                  State := State + 1;
               when 5 =>
                  wb3_adr_i <= X"05";
                                                wb3_we_i <= '0';
                  WaitACKWB := '1';
                  State := State + 1;
               when 6 =>
                  State := State + 1;
               when 7 =>
                  State := State + 1;
               when 8 =>
                  wb3_adr_i <= X"01";
                  wb3_dat_i <= data;
                                                wb3_we_i <= '1';
                  WaitACKWB := '1';
                  State := 0;
               when others =>
                  null;
            end case;
 
            if (WaitACKWB = '1') then
               wb3_stb_i <= '1';
               wb3_cyc_i <= '1';
            end if;
         end if;
      end if;
   end process wb3_control;
 
 
 
   wb_rst_i <= '1', '0' after 60 ns; --active high
 
        Clocking : process --50 MHz -> T = 20 ns 
        begin
                        wb_clk_i <= '1';
                        wait for 10 ns;
                        wb_clk_i <= '0';
                        wait for 10 ns;
        end process;
 
END;

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Subversion Repositories copyblaze

[/] [copyblaze/] [trunk/] [copyblaze/] [rtl/] [vhdl/] [ip/] [wb_3p_spram_wrapper/] [tb_wb_Np_ram.vhd] - Blame information for rev 65

Line No.	Rev	Author	Line
1	65	ameziti	`----------------------------------------------------------------------------------`
2			`-- Company: VISENGI S.L. (www.visengi.com)`
3			`-- Engineer: Victor Lopez Lorenzo (victor.lopez (at) visengi (dot) com)`
4			`--`
5			`-- Create Date: 23:44:13 22/August/2008`
6			`-- Project Name: Triple Port WISHBONE SPRAM Wrapper`
7			`-- Tool versions: Xilinx ISE 9.2i`
8			`-- Description:`
9			`--`
10			`-- Description: This is a wrapper for an inferred single port RAM, that converts it`
11			`-- into a Three-port RAM with one WISHBONE slave interface for each port.`
12			`--`
13			`--`
14			`-- LICENSE TERMS: GNU LESSER GENERAL PUBLIC LICENSE Version 2.1`
15			`-- That is you may use it in ANY project (commercial or not) without paying a cent.`
16			`-- You are only required to include in the copyrights/about section of accompanying`
17			`-- software and manuals of use that your system contains a "3P WB SPRAM Wrapper`
18			`-- (C) VISENGI S.L. under LGPL license"`
19			`-- This holds also in the case where you modify the core, as the resulting core`
20			`-- would be a derived work.`
21			`-- Also, we would like to know if you use this core in a project of yours, just an email will do.`
22			`--`
23			`-- Please take good note of the disclaimer section of the LPGL license, as we don't`
24			`-- take any responsability for anything that this core does.`
25			`----------------------------------------------------------------------------------`
26
27			`LIBRARY ieee;`
28			`USE ieee.std_logic_1164.ALL;`
29			`USE ieee.std_logic_unsigned.all;`
30			`USE ieee.numeric_std.ALL;`
31
32			`ENTITY tb_wb_Np_ram_vhd IS`
33			`END tb_wb_Np_ram_vhd;`
34
35			`ARCHITECTURE behavior OF tb_wb_Np_ram_vhd IS`
36
37			`-- Component Declaration for the Unit Under Test (UUT)`
38			`COMPONENT wb_Np_ram`
39			`PORT(`
40			`wb_clk_i : IN std_logic;`
41			`wb_rst_i : IN std_logic;`
42			`wb1_cyc_i : IN std_logic;`
43			`wb1_stb_i : IN std_logic;`
44			`wb1_we_i : IN std_logic;`
45			`wb1_adr_i : IN std_logic_vector(7 downto 0);`
46			`wb1_dat_i : IN std_logic_vector(31 downto 0);`
47			`wb2_cyc_i : IN std_logic;`
48			`wb2_stb_i : IN std_logic;`
49			`wb2_we_i : IN std_logic;`
50			`wb2_adr_i : IN std_logic_vector(7 downto 0);`
51			`wb2_dat_i : IN std_logic_vector(31 downto 0);`
52			`wb3_cyc_i : IN std_logic;`
53			`wb3_stb_i : IN std_logic;`
54			`wb3_we_i : IN std_logic;`
55			`wb3_adr_i : IN std_logic_vector(7 downto 0);`
56			`wb3_dat_i : IN std_logic_vector(31 downto 0);`
57			`wb1_dat_o : OUT std_logic_vector(31 downto 0);`
58			`wb1_ack_o : OUT std_logic;`
59			`wb2_dat_o : OUT std_logic_vector(31 downto 0);`
60			`wb2_ack_o : OUT std_logic;`
61			`wb3_dat_o : OUT std_logic_vector(31 downto 0);`
62			`wb3_ack_o : OUT std_logic`
63			`);`
64			`END COMPONENT;`
65
66			`--Inputs`
67			`SIGNAL wb_clk_i : std_logic := '0';`
68			`SIGNAL wb_rst_i : std_logic := '0';`
69			`SIGNAL wb1_cyc_i : std_logic := '0';`
70			`SIGNAL wb1_stb_i : std_logic := '0';`
71			`SIGNAL wb1_we_i : std_logic := '0';`
72			`SIGNAL wb2_cyc_i : std_logic := '0';`
73			`SIGNAL wb2_stb_i : std_logic := '0';`
74			`SIGNAL wb2_we_i : std_logic := '0';`
75			`SIGNAL wb3_cyc_i : std_logic := '0';`
76			`SIGNAL wb3_stb_i : std_logic := '0';`
77			`SIGNAL wb3_we_i : std_logic := '0';`
78			`SIGNAL wb1_adr_i : std_logic_vector(7 downto 0) := (others=>'0');`
79			`SIGNAL wb1_dat_i : std_logic_vector(31 downto 0) := (others=>'0');`
80			`SIGNAL wb2_adr_i : std_logic_vector(7 downto 0) := (others=>'0');`
81			`SIGNAL wb2_dat_i : std_logic_vector(31 downto 0) := (others=>'0');`
82			`SIGNAL wb3_adr_i : std_logic_vector(7 downto 0) := (others=>'0');`
83			`SIGNAL wb3_dat_i : std_logic_vector(31 downto 0) := (others=>'0');`
84
85			`--Outputs`
86			`SIGNAL wb1_dat_o : std_logic_vector(31 downto 0);`
87			`SIGNAL wb1_ack_o : std_logic;`
88			`SIGNAL wb2_dat_o : std_logic_vector(31 downto 0);`
89			`SIGNAL wb2_ack_o : std_logic;`
90			`SIGNAL wb3_dat_o : std_logic_vector(31 downto 0);`
91			`SIGNAL wb3_ack_o : std_logic;`
92
93			`BEGIN`
94
95			`-- Instantiate the Unit Under Test (UUT)`
96			`uut: wb_Np_ram PORT MAP(`
97			`wb_clk_i => wb_clk_i,`
98			`wb_rst_i => wb_rst_i,`
99			`wb1_cyc_i => wb1_cyc_i,`
100			`wb1_stb_i => wb1_stb_i,`
101			`wb1_we_i => wb1_we_i,`
102			`wb1_adr_i => wb1_adr_i,`
103			`wb1_dat_i => wb1_dat_i,`
104			`wb1_dat_o => wb1_dat_o,`
105			`wb1_ack_o => wb1_ack_o,`
106			`wb2_cyc_i => wb2_cyc_i,`
107			`wb2_stb_i => wb2_stb_i,`
108			`wb2_we_i => wb2_we_i,`
109			`wb2_adr_i => wb2_adr_i,`
110			`wb2_dat_i => wb2_dat_i,`
111			`wb2_dat_o => wb2_dat_o,`
112			`wb2_ack_o => wb2_ack_o,`
113			`wb3_cyc_i => wb3_cyc_i,`
114			`wb3_stb_i => wb3_stb_i,`
115			`wb3_we_i => wb3_we_i,`
116			`wb3_adr_i => wb3_adr_i,`
117			`wb3_dat_i => wb3_dat_i,`
118			`wb3_dat_o => wb3_dat_o,`
119			`wb3_ack_o => wb3_ack_o`
120			`);`
121
122
123
124
125
126
127			`wb1_control : process (wb_rst_i, wb_clk_i)`
128			`variable WaitACKWB : std_logic;`
129			`variable data : std_logic_vector(31 downto 0);`
130			`variable State : integer;`
131			`begin`
132			`if (wb_rst_i = '1') then`
133			`wb1_dat_i <= (others => '0');`
134			`wb1_adr_i <= (others => '0');`
135			`wb1_we_i <= '0';`
136			`wb1_stb_i <= '0';`
137			`wb1_cyc_i <= '0';`
138
139			`data := (others => '0');`
140			`WaitACKWB := '0';`
141			`State := 0;`
142			`elsif (wb_clk_i = '1' and wb_clk_i'event) then`
143			`if (WaitACKWB = '1') then`
144			`if (wb1_ack_o = '1') then`
145			`WaitACKWB := '0';`
146			`wb1_we_i <= '0';`
147			`wb1_stb_i <= '0';`
148			`wb1_cyc_i <= '0';`
149			`data := wb1_dat_o;`
150			`end if;`
151			`end if;`
152
153			`if (WaitACKWB = '0') then`
154			`case State is`
155			`when 0 => --init`
156			`wb1_adr_i <= X"00";`
157			`wb1_dat_i <= x"00000001";`
158			`wb1_we_i <= '1';`
159			`WaitACKWB := '1';`
160			`State := State + 1;`
161			`when 1 =>`
162			`wb1_adr_i <= X"01";`
163			`wb1_dat_i <= x"00000002";`
164			`wb1_we_i <= '1';`
165			`WaitACKWB := '1';`
166			`State := State + 1;`
167			`when 2 =>`
168			`wb1_adr_i <= X"02";`
169			`wb1_dat_i <= x"00000003";`
170			`wb1_we_i <= '1';`
171			`WaitACKWB := '1';`
172			`State := State + 1;`
173			`when 3 =>`
174			`State := State + 1;`
175			`when 4 =>`
176			`wb1_adr_i <= X"00";`
177			`wb1_we_i <= '0';`
178			`WaitACKWB := '1';`
179			`State := State + 1;`
180			`when 5 =>`
181			`State := State + 1;`
182			`when 6 =>`
183			`State := State + 1;`
184			`when 7 =>`
185			`wb1_adr_i <= X"01";`
186			`wb1_dat_i <= data;`
187			`wb1_we_i <= '1';`
188			`WaitACKWB := '1';`
189			`State := State + 1;`
190			`when 8 =>`
191			`wb1_adr_i <= X"05";`
192			`wb1_dat_i <= x"00500FA0";`
193			`wb1_we_i <= '1';`
194			`WaitACKWB := '1';`
195			`State := 0;`
196			`when 45 =>`
197			`report "-----------> Testbench Finished OK!" severity FAILURE; --everything went fine, it's just to stop the simulation`
198
199			`when others =>`
200			`null;`
201			`end case;`
202
203			`if (WaitACKWB = '1') then`
204			`wb1_stb_i <= '1';`
205			`wb1_cyc_i <= '1';`
206			`end if;`
207			`end if;`
208			`end if;`
209			`end process wb1_control;`
210
211
212
213
214
215			`wb2_control : process (wb_rst_i, wb_clk_i)`
216			`variable WaitACKWB : std_logic;`
217			`variable data : std_logic_vector(31 downto 0);`
218			`variable State : integer;`
219			`begin`
220			`if (wb_rst_i = '1') then`
221			`wb2_dat_i <= (others => '0');`
222			`wb2_adr_i <= (others => '0');`
223			`wb2_we_i <= '0';`
224			`wb2_stb_i <= '0';`
225			`wb2_cyc_i <= '0';`
226
227			`data := (others => '0');`
228			`WaitACKWB := '0';`
229			`State := 0;`
230			`elsif (wb_clk_i = '1' and wb_clk_i'event) then`
231			`if (WaitACKWB = '1') then`
232			`if (wb2_ack_o = '1') then`
233			`WaitACKWB := '0';`
234			`wb2_we_i <= '0';`
235			`wb2_stb_i <= '0';`
236			`wb2_cyc_i <= '0';`
237			`data := wb2_dat_o;`
238			`end if;`
239			`end if;`
240
241			`if (WaitACKWB = '0') then`
242			`case State is`
243			`when 0 => --init`
244			`wb2_adr_i <= X"05";`
245			`wb2_we_i <= '0';`
246			`WaitACKWB := '1';`
247			`State := State + 1;`
248			`when 1 =>`
249			`State := State + 1;`
250			`when 2 =>`
251			`State := State + 1;`
252			`when 3 =>`
253			`State := State + 1;`
254			`when 4 =>`
255			`wb2_adr_i <= X"04";`
256			`wb2_dat_i <= x"00000002";`
257			`wb2_we_i <= '1';`
258			`WaitACKWB := '1';`
259			`State := State + 1;`
260			`when 5 =>`
261			`State := State + 1;`
262			`when 6 =>`
263			`State := State + 1;`
264			`when 7 =>`
265			`State := State + 1;`
266			`when 8 =>`
267			`wb2_adr_i <= X"03";`
268			`wb2_we_i <= '0';`
269			`WaitACKWB := '1';`
270			`State := State + 1;`
271			`when 9 =>`
272			`State := State + 1;`
273			`when 10 =>`
274			`wb2_adr_i <= X"02";`
275			`wb2_we_i <= '0';`
276			`WaitACKWB := '1';`
277			`State := State + 1;`
278			`when 11 =>`
279			`State := State + 1;`
280			`when 12 =>`
281			`State := State + 1;`
282			`when 13 =>`
283			`State := State + 1;`
284			`when 14 =>`
285			`wb2_adr_i <= X"01";`
286			`wb2_we_i <= '0';`
287			`WaitACKWB := '1';`
288			`State := State + 1;`
289			`when 15 =>`
290			`State := State + 1;`
291			`when 16 =>`
292			`State := State + 1;`
293			`when 17 =>`
294			`wb2_adr_i <= X"05";`
295			`wb2_dat_i <= data;`
296			`wb2_we_i <= '1';`
297			`WaitACKWB := '1';`
298			`State := 0;`
299			`when others =>`
300			`null;`
301			`end case;`
302
303			`if (WaitACKWB = '1') then`
304			`wb2_stb_i <= '1';`
305			`wb2_cyc_i <= '1';`
306			`end if;`
307			`end if;`
308			`end if;`
309			`end process wb2_control;`
310
311
312
313			`wb3_control : process (wb_rst_i, wb_clk_i)`
314			`variable WaitACKWB : std_logic;`
315			`variable data : std_logic_vector(31 downto 0);`
316			`variable State : integer;`
317			`begin`
318			`if (wb_rst_i = '1') then`
319			`wb3_dat_i <= (others => '0');`
320			`wb3_adr_i <= (others => '0');`
321			`wb3_we_i <= '0';`
322			`wb3_stb_i <= '0';`
323			`wb3_cyc_i <= '0';`
324
325			`data := (others => '0');`
326			`WaitACKWB := '0';`
327			`State := 0;`
328			`elsif (wb_clk_i = '1' and wb_clk_i'event) then`
329			`if (WaitACKWB = '1') then`
330			`if (wb3_ack_o = '1') then`
331			`WaitACKWB := '0';`
332			`wb3_we_i <= '0';`
333			`wb3_stb_i <= '0';`
334			`wb3_cyc_i <= '0';`
335			`data := wb3_dat_o;`
336			`end if;`
337			`end if;`
338
339			`if (WaitACKWB = '0') then`
340			`case State is`
341			`when 0 =>`
342			`State := State + 1;`
343			`when 1 => --init`
344			`wb3_adr_i <= X"05";`
345			`wb3_we_i <= '0';`
346			`WaitACKWB := '1';`
347			`State := State + 1;`
348			`when 2 =>`
349			`wb3_adr_i <= X"02";`
350			`wb3_dat_i <= x"00000002";`
351			`wb3_we_i <= '1';`
352			`WaitACKWB := '1';`
353			`State := State + 1;`
354			`when 3 =>`
355			`State := State + 1;`
356			`when 4 =>`
357			`wb3_adr_i <= X"01";`
358			`wb3_dat_i <= x"00000003";`
359			`wb3_we_i <= '1';`
360			`WaitACKWB := '1';`
361			`State := State + 1;`
362			`when 5 =>`
363			`wb3_adr_i <= X"05";`
364			`wb3_we_i <= '0';`
365			`WaitACKWB := '1';`
366			`State := State + 1;`
367			`when 6 =>`
368			`State := State + 1;`
369			`when 7 =>`
370			`State := State + 1;`
371			`when 8 =>`
372			`wb3_adr_i <= X"01";`
373			`wb3_dat_i <= data;`
374			`wb3_we_i <= '1';`
375			`WaitACKWB := '1';`
376			`State := 0;`
377			`when others =>`
378			`null;`
379			`end case;`
380
381			`if (WaitACKWB = '1') then`
382			`wb3_stb_i <= '1';`
383			`wb3_cyc_i <= '1';`
384			`end if;`
385			`end if;`
386			`end if;`
387			`end process wb3_control;`
388
389
390
391			`wb_rst_i <= '1', '0' after 60 ns; --active high`
392
393			`Clocking : process --50 MHz -> T = 20 ns`
394			`begin`
395			`wb_clk_i <= '1';`
396			`wait for 10 ns;`
397			`wb_clk_i <= '0';`
398			`wait for 10 ns;`
399			`end process;`
400
401			`END;`