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[/] [csa/] [trunk/] [bench/] [decrypt_tb.v] - Blame information for rev 41

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// this is the test bench for decrypt module
 
 
`include "../bench/timescale.v"
 
module decrypt_tb;
 
reg clk;
reg rst;
 
 
 
integer bytes;
integer out_bytes;
integer offset;
 
reg      [  8*8-1   : 0]  even_cw;
reg      [  8*8-1   : 0]  odd_cw;
reg      [    8-1   : 0]  encrypted_byte;
 
reg      [8*8-1:0]    ck;
reg                   even_odd;
reg                   en;
reg                   key_en;
reg      [  8-1:0]    enc;
wire     [  8-1:0]    dec;
wire                  valid;
 
initial
begin
        $read_data(
                                "../test_dat/decrypt.in"
                               ,even_cw
                  );
 
        $read_data(
                                "../test_dat/decrypt.in"
                               ,8
                               ,even_cw
                  );
 
        encrypted_byte=8'h00; // or can not read data
        out_bytes = 1;
 
        en=0;
        key_en=0;
 
        repeat(14)@(posedge clk);
 
        // set even cw 
        @(posedge clk);
        ck=even_cw;
        en=0;
        even_odd=0;
        @(posedge clk);
        key_en=1;
        @(posedge clk);
        key_en=0;
        repeat (11) @(posedge clk);
 
        // set odd key
        @(posedge clk);
        ck=odd_cw;
        key_en=1;
        en=0;
        even_odd=1;
        @(posedge clk);
        key_en=0;
        repeat (11)@(posedge clk);
 
        repeat(4)@(posedge clk);
 
        // decrypt
        for(bytes=1;bytes<=188;bytes=bytes+1)
        begin
                offset=16+(bytes-1);
                $read_data(
                                   "../test_dat/decrypt.in"
                                ,  offset
                                ,  encrypted_byte
                        );
                enc=encrypted_byte;
                en=1;
              //  @(posedge clk);
              //  en=0;
                @(posedge clk);
        end
 
        repeat(44) @(posedge clk);
 
 
        $stop;
 
end
 
always @(posedge clk)
        if(valid)
        begin
                if(out_bytes==1)
                begin
        $write_data(
                                 "../test_dat/decrypt.out.v"
                                ,dec
                   );
                end
                else
                begin
        $write_data(
                                 "../test_dat/decrypt.out.v"
                                ,"a"
                                ,dec
                   );
                end
                out_bytes=out_bytes+1;
        end
 
 
decrypt b(
                  .clk        (clk)
                , .rst        (rst)
                , .ck         (ck)
                , .key_en     (key_en)
                , .even_odd   (even_odd)
                , .en         (en)
                , .encrypted  (enc)
                , .decrypted  (dec)
                , .valid      (valid)
                );
 
 
 
 
initial
begin
        clk<=1'b0;
        forever #5 clk=~clk;
end
 
initial
begin
        rst<=1'b1;
        @(posedge clk);
        @(posedge clk);
        rst=1'h0;
end
endmodule

Line No.	Rev	Author	Line
1	18	simon111
2			`// this is the test bench for decrypt module`
3
4	22	simon111
5	40	simon111	`include "../bench/timescale.v"
6	22	simon111
7	20	simon111	`module decrypt_tb;`
8	18	simon111
9	22	simon111	`reg clk;`
10			`reg rst;`
11
12
13
14			`integer bytes;`
15			`integer out_bytes;`
16	41	simon111	`integer offset;`
17	22	simon111
18	40	simon111	`reg [ 8*8-1 : 0] even_cw;`
19			`reg [ 8*8-1 : 0] odd_cw;`
20	41	simon111	`reg [ 8-1 : 0] encrypted_byte;`
21	22	simon111
22			`reg [8*8-1:0] ck;`
23			`reg even_odd;`
24			`reg en;`
25			`reg key_en;`
26			`reg [ 8-1:0] enc;`
27			`wire [ 8-1:0] dec;`
28	41	simon111	`wire valid;`
29	22	simon111
30	18	simon111	`initial`
31			`begin`
32			`$read_data(`
33	22	simon111	`"../test_dat/decrypt.in"`
34	40	simon111	`,even_cw`
35	18	simon111	`);`
36
37	40	simon111	`$read_data(`
38			`"../test_dat/decrypt.in"`
39			`,8`
40			`,even_cw`
41			`);`
42
43	41	simon111	`encrypted_byte=8'h00; // or can not read data`
44	22	simon111	`out_bytes = 1;`
45	18	simon111
46	22	simon111	`en=0;`
47			`key_en=0;`
48
49	23	simon111	`repeat(14)@(posedge clk);`
50	22	simon111
51			`// set even cw`
52			`@(posedge clk);`
53			`ck=even_cw;`
54			`en=0;`
55			`even_odd=0;`
56			`@(posedge clk);`
57			`key_en=1;`
58			`@(posedge clk);`
59			`key_en=0;`
60			`repeat (11) @(posedge clk);`
61
62			`// set odd key`
63			`@(posedge clk);`
64			`ck=odd_cw;`
65			`key_en=1;`
66			`en=0;`
67			`even_odd=1;`
68			`@(posedge clk);`
69			`key_en=0;`
70			`repeat (11)@(posedge clk);`
71	41	simon111
72	22	simon111	`repeat(4)@(posedge clk);`
73
74			`// decrypt`
75			`for(bytes=1;bytes<=188;bytes=bytes+1)`
76			`begin`
77	41	simon111	`offset=16+(bytes-1);`
78			`$read_data(`
79			`"../test_dat/decrypt.in"`
80			`, offset`
81			`, encrypted_byte`
82			`);`
83			`enc=encrypted_byte;`
84	22	simon111	`en=1;`
85	41	simon111	`// @(posedge clk);`
86			`// en=0;`
87	22	simon111	`@(posedge clk);`
88			`end`
89
90			`repeat(44) @(posedge clk);`
91
92	41	simon111
93			`$stop;`
94
95			`end`
96
97			`always @(posedge clk)`
98			`if(valid)`
99			`begin`
100			`if(out_bytes==1)`
101			`begin`
102	18	simon111	`$write_data(`
103	22	simon111	`"../test_dat/decrypt.out.v"`
104	41	simon111	`,dec`
105	18	simon111	`);`
106	41	simon111	`end`
107			`else`
108			`begin`
109	22	simon111	`$write_data(`
110			`"../test_dat/decrypt.out.v"`
111			`,"a"`
112	41	simon111	`,dec`
113	22	simon111	`);`
114	41	simon111	`end`
115	22	simon111	`out_bytes=out_bytes+1;`
116			`end`
117
118
119	20	simon111	`decrypt b(`
120	22	simon111	`.clk (clk)`
121			`, .rst (rst)`
122			`, .ck (ck)`
123			`, .key_en (key_en)`
124			`, .even_odd (even_odd)`
125			`, .en (en)`
126			`, .encrypted (enc)`
127			`, .decrypted (dec)`
128	41	simon111	`, .valid (valid)`
129	18	simon111	`);`
130	22	simon111
131
132
133
134			`initial`
135			`begin`
136			`clk<=1'b0;`
137			`forever #5 clk=~clk;`
138			`end`
139
140			`initial`
141			`begin`
142			`rst<=1'b1;`
143			`@(posedge clk);`
144			`@(posedge clk);`
145			`rst=1'h0;`
146			`end`
147	18	simon111	`endmodule`

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[/] [csa/] [trunk/] [bench/] [decrypt_tb.v] - Blame information for rev 41