Subversion Repositories csa

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////  cas core                                                   ////

////                                                             ////

////  Author: Simon Panti                                        ////

////          mengxipeng@gmail.com                               ////

////                                                             ////

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//// Copyright (C) 2007 Simon Panti                              ////

////                    mengxipeng@gmail.com                     ////

////                                                             ////

//// This source file may be used and distributed without        ////

//// restriction provided that this copyright statement is not   ////

//// removed from the file and that any derivative work contains ////

//// the original copyright notice and the associated disclaimer.////

////                                                             ////

////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////

//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////

//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////

//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////

//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////

//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////

//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////

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csa core

===============

attached is a cas core implementation in verilog. it implement

a cas descrambler

reference:

                csa.c and csa.h in vlc opensource project.

archecture

===============

the top module is the group_decrypt.

Status

======

7-sep-2007      added key csa_ComputeKey

4-May-2009      group_decrypt module pass modelsim basicly

How to test this core

========================

this project mainly has three dictories:

     rtl bench and sw_sim

every module have a file in these dictories

i simualted my modules by open source program veriwell and iverilog in the early time , but

they don't work well, and generate some error result sometime. so i use the modelsim now.

1) generate test data

   cd   

   make MODULE= preare_    ( for example: make MODULE=group_decrypt preare_group_decrypt )

   this command will generate a binary file  /test_dat/.in

   (for example: test_dat/group_decrypt.in )

2) software simulate

   cd  /sw_sim

   make MODULE= tt

   this command will compile  and run the module test program

   and will generate a binary output file /test_dat/.out.sw

   (for example: test_dat/group_decrypt.out.sw )

3) run test bench

   start the modelsim      (i use the modelsim 6.2b LE)

   cd  /modelsim6.2b

   run .do tcl script,  ( for example: do group_decrypt.do )

   and will generate a binary output file /test_dat/.out.v

if the two output file is same, this module is pass

Directory Structure

===================

[core_root]

 |

 +-doc                        Documentation

 |

 +-bench--+                   Test Bench

 |

 +-rtl----+                   Core RTL Sources

 |

 +-modelsim6.2b--+            modelsim files

 |

 +-quartus10--+               altera quartus 10.1 project file

 |

 +-sw_sim-----+               the pc programs for generate some test data

 |

 +-test_data--+               the test datas for test bench

about the author

================

if you have some issues and advance, please contact me:

 mengxipeng@gmail.com