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[/] [csa/] [trunk/] [quartus10/] [csa.qsf] - Blame information for rev 44

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1 28 simon111 
# Copyright (C) 1991-2008 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors.  Please refer to the
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# applicable agreement for further details.
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# The default values for assignments are stored in the file
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#               csa_assignment_defaults.qdf
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# If this file doesn't exist, and for assignments not listed, see file
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#               assignment_defaults.qdf
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# Altera recommends that you do not modify this file. This
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# file is updated automatically by the Quartus II software
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# and any changes you make may be lost or overwritten.
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set_global_assignment -name FAMILY Cyclone
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set_global_assignment -name DEVICE EP1C6Q240C8
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set_global_assignment -name TOP_LEVEL_ENTITY csa_fpga
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:03:51  APRIL 15, 2009"
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set_global_assignment -name LAST_QUARTUS_VERSION 8.1
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set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name LL_ROOT_REGION ON -entity csa -section_id "Root Region"
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set_global_assignment -name LL_MEMBER_STATE LOCKED -entity csa -section_id "Root Region"
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set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
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set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
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set_location_assignment PIN_224 -to fifoadr[0]
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set_location_assignment PIN_223 -to fifoadr[1]
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set_location_assignment PIN_208 -to fd[0]
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set_location_assignment PIN_213 -to fd[1]
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set_location_assignment PIN_214 -to fd[2]
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set_location_assignment PIN_215 -to fd[3]
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set_location_assignment PIN_236 -to fd[4]
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set_location_assignment PIN_235 -to fd[5]
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set_location_assignment PIN_234 -to fd[6]
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set_location_assignment PIN_233 -to fd[7]
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set_location_assignment PIN_220 -to fd[8]
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set_location_assignment PIN_219 -to fd[9]
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set_location_assignment PIN_218 -to fd[10]
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set_location_assignment PIN_217 -to fd[11]
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set_location_assignment PIN_216 -to fd[12]
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set_location_assignment PIN_202 -to fd[13]
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set_location_assignment PIN_203 -to fd[14]
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set_location_assignment PIN_204 -to fd[15]
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set_location_assignment PIN_222 -to pktend
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set_location_assignment PIN_221 -to slcs
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set_location_assignment PIN_225 -to sloe
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set_location_assignment PIN_205 -to slrd
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set_location_assignment PIN_206 -to slwr
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set_location_assignment PIN_28 -to clk
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set_location_assignment PIN_66 -to bell
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set_location_assignment PIN_226 -to flagc
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set_location_assignment PIN_207 -to ifclk
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set_location_assignment PIN_227 -to flagb
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set_location_assignment PIN_228 -to flaga
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set_location_assignment PIN_134 -to led[0]
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set_location_assignment PIN_135 -to led[1]
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set_location_assignment PIN_136 -to led[2]
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set_location_assignment PIN_137 -to led[3]
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set_location_assignment PIN_138 -to led[4]
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set_location_assignment PIN_139 -to led[5]
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set_location_assignment PIN_140 -to led[6]
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set_location_assignment PIN_141 -to led[7]
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set_location_assignment PIN_156 -to rst
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set_location_assignment PIN_60 -to ledseg[0]
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set_location_assignment PIN_61 -to ledseg[1]
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set_location_assignment PIN_62 -to ledseg[2]
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set_location_assignment PIN_63 -to ledseg[3]
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set_location_assignment PIN_59 -to seg_d[0]
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set_location_assignment PIN_58 -to seg_d[5]
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set_location_assignment PIN_57 -to seg_d[1]
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set_location_assignment PIN_56 -to seg_d[6]
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set_location_assignment PIN_55 -to seg_d[2]
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set_location_assignment PIN_54 -to seg_d[7]
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set_location_assignment PIN_53 -to seg_d[3]
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set_location_assignment PIN_50 -to seg_d[4]
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set_global_assignment -name USE_SIGNALTAP_FILE csa.stp
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set_global_assignment -name ENABLE_SIGNALTAP ON
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set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0
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set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to ifclk -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=128" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=128" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0
112 39 simon111 
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
113 44 simon111 
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to bell -section_id auto_signaltap_0
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set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to bell -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=1" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=1" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=000000000000000000000000" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=24" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=65169" -section_id auto_signaltap_0
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set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=13610" -section_id auto_signaltap_0
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set_global_assignment -name VERILOG_FILE usb_cnt.v
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set_global_assignment -name VERILOG_FILE ../rtl/key_cnt.v
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set_global_assignment -name VERILOG_FILE ../rtl/group_decrypt.v
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set_global_assignment -name VERILOG_FILE ../rtl/ts_serial_out.v
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set_global_assignment -name VERILOG_FILE ../rtl/ts_sync.v
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set_global_assignment -name VERILOG_FILE ledseg_cnt.v
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set_global_assignment -name VERILOG_FILE led_cnt.v
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set_global_assignment -name VERILOG_FILE hex2seg.v
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set_global_assignment -name SIGNALTAP_FILE csa.stp
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set_global_assignment -name VERILOG_FILE ../rtl/sbox1.v
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set_global_assignment -name VERILOG_FILE ../rtl/sbox2.v
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set_global_assignment -name VERILOG_FILE ../rtl/sbox3.v
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set_global_assignment -name VERILOG_FILE ../rtl/sbox4.v
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set_global_assignment -name VERILOG_FILE ../rtl/sbox5.v
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set_global_assignment -name VERILOG_FILE ../rtl/sbox6.v
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set_global_assignment -name VERILOG_FILE ../rtl/sbox7.v
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set_global_assignment -name VERILOG_FILE ../rtl/sboxes.v
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set_global_assignment -name VERILOG_FILE ../rtl/stream_iteration.v
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set_global_assignment -name VERILOG_FILE ../rtl/stream_byte.v
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set_global_assignment -name VERILOG_FILE ../rtl/stream_8bytes.v
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set_global_assignment -name VERILOG_FILE ../rtl/key_perm.v
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set_global_assignment -name VERILOG_FILE ../rtl/block_perm.v
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set_global_assignment -name VERILOG_FILE ../rtl/block_sbox.v
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set_global_assignment -name VERILOG_FILE ../rtl/stream_cypher.v
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set_global_assignment -name VERILOG_FILE ../rtl/key_schedule.v
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set_global_assignment -name VERILOG_FILE ../rtl/block_decypher.v
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set_global_assignment -name VERILOG_FILE ../rtl/decrypt.v
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set_global_assignment -name VERILOG_FILE csa_fpga.v

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