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[/] [csa/] [trunk/] [quartus10/] [csa_fpga.v] - Blame information for rev 30

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// this file is the test circuit
// author: Simom Panti
//
 
 
module csa_fpga(
                          output              bell
                        , input               clk
                        , input               rst
                        , input               flaga
                        , input               flagb
                        , input               flagc
                        , output              slcs
                        , output              pktend
                        , output reg          sloe
                        , output reg          slwr
                        , output reg          slrd
                        , output reg [ 1:0]   fifoadr
                        , inout      [15:0]   fd
                        , input               ifclk
                        , output     [ 7:0]   led
                        , output     [ 3:0]   ledseg
                        , output     [ 7:0]   seg_d
             );
 
 
        wire usbclk = ifclk;
        wire ep6_havedata = flaga;
        wire ep2_haveroom = flagc;
        wire ep8_havedata = flagb;
 
        assign bell = 1'h1;
 
`define CNT_WIDTH 25
`define STA_WIDTH 4
 
        ////////////////////////////////////////////////////////////////////////////////
        // led control
        ////////////////////////////////////////////////////////////////////////////////
        reg [`CNT_WIDTH-1:0]led_cnt;
 
        always @(posedge usbclk)
                led_cnt <= led_cnt + `CNT_WIDTH'h00001;
 
        wire sec_clk = led_cnt[`CNT_WIDTH-1];
 
        led_cnt led1(
                         .clk    (usbclk)
                       , .rst    (rst)
                       , .scan   (sec_clk)
                       , .led    (led)
                        );
 
 
        wire seg_clk = led_cnt[`CNT_WIDTH-16];
        ledseg_cnt ledseg1(
                         .clk      (usbclk)
                       , .rst      (rst)
                       , .scan     (seg_clk)
                       , .data     (usb_dat_in)
                       , .seg      (ledseg)
                       , .segd     (seg_d)
                        );
 
        ////////////////////////////////////////////////////////////////////////////////
        // usb interface
        ////////////////////////////////////////////////////////////////////////////////
        assign slcs  =1'h0;
        assign pktend=1'h1;
 
`define EP2_W  2'h0
`define EP6_R  2'h1
`define EP8_R  2'h2
`define NO_ACT 2'h3
 
        reg [ 1:0] last_action;
        reg [15:0] usb_dat_out;
        reg [15:0] usb_dat_in;
 
        always @(posedge usbclk)
                if(ep6_havedata)
                begin
                        sloe<=1'h0;
                        fifoadr<=2'h2;
                        slrd<=1'h0;
                        slwr<=1'h1;
                        last_action<=`EP6_R;
                end
                else
                if(ep8_havedata)
                begin
                        sloe<=1'h0;
                        fifoadr<=2'h3;
                        slrd<=1'h0;
                        slwr<=1'h1;
                        last_action<=`EP8_R;
                end
                else
                if(ep2_haveroom)
                begin
                        // ouput data
                        sloe<=1'h1;
                        fifoadr<=2'h0;
                        slwr<=1'h0;
                        slrd<=1'h1;
                        last_action<=`EP2_W;
 
                end
                else
                begin
                        sloe<=1'h1;
                        fifoadr<=2'h0;
                        slwr<=1'h1;
                        slrd<=1'h1;
                        last_action<=`NO_ACT;
                end
 
        always @(posedge usbclk)
                if(last_action==`EP8_R )
                        usb_dat_in<=fd;
 
        assign fd=(sloe)?usb_dat_out:16'hzzzz;
 
        ////////////////////////////////////////////////////////////////////////////////
        // csa decrypt module
        ////////////////////////////////////////////////////////////////////////////////
        decrypt csa_decrypt(
                                 . clk            (usbclk)
                                ,. rst            (rst)
                                ,. ck             (64'h0000000000000000)
                                ,. key_en         (1'h0)
                                ,. even_odd       (1'h0)
                                ,. en             ()
                                ,. encrypted      ()
                                ,. decrypted      ()
                                ,. invalid        ()
                    );
 
 
endmodule
 

Line No.	Rev	Author	Line
1	28	simon111
2
3			`// this file is the test circuit`
4			`// author: Simom Panti`
5			`//`
6
7
8			`module csa_fpga(`
9			`output bell`
10			`, input clk`
11			`, input rst`
12			`, input flaga`
13			`, input flagb`
14			`, input flagc`
15			`, output slcs`
16			`, output pktend`
17			`, output reg sloe`
18			`, output reg slwr`
19			`, output reg slrd`
20			`, output reg [ 1:0] fifoadr`
21			`, inout [15:0] fd`
22			`, input ifclk`
23			`, output [ 7:0] led`
24			`, output [ 3:0] ledseg`
25			`, output [ 7:0] seg_d`
26			`);`
27
28
29			`wire usbclk = ifclk;`
30			`wire ep6_havedata = flaga;`
31			`wire ep2_haveroom = flagc;`
32	30	simon111	`wire ep8_havedata = flagb;`
33	28	simon111
34			`assign bell = 1'h1;`
35
36			`define CNT_WIDTH 25
37			`define STA_WIDTH 4
38
39			`////////////////////////////////////////////////////////////////////////////////`
40			`// led control`
41			`////////////////////////////////////////////////////////////////////////////////`
42			reg [`CNT_WIDTH-1:0]led_cnt;
43
44			`always @(posedge usbclk)`
45			led_cnt <= led_cnt + `CNT_WIDTH'h00001;
46
47			wire sec_clk = led_cnt[`CNT_WIDTH-1];
48
49			`led_cnt led1(`
50			`.clk (usbclk)`
51			`, .rst (rst)`
52			`, .scan (sec_clk)`
53			`, .led (led)`
54			`);`
55
56
57			wire seg_clk = led_cnt[`CNT_WIDTH-16];
58			`ledseg_cnt ledseg1(`
59			`.clk (usbclk)`
60			`, .rst (rst)`
61			`, .scan (seg_clk)`
62	30	simon111	`, .data (usb_dat_in)`
63	28	simon111	`, .seg (ledseg)`
64			`, .segd (seg_d)`
65			`);`
66
67			`////////////////////////////////////////////////////////////////////////////////`
68			`// usb interface`
69			`////////////////////////////////////////////////////////////////////////////////`
70	30	simon111	`assign slcs =1'h0;`
71			`assign pktend=1'h1;`
72	28	simon111
73	30	simon111	`define EP2_W 2'h0
74			`define EP6_R 2'h1
75			`define EP8_R 2'h2
76			`define NO_ACT 2'h3
77	28	simon111
78	30	simon111	`reg [ 1:0] last_action;`
79			`reg [15:0] usb_dat_out;`
80			`reg [15:0] usb_dat_in;`
81	28	simon111
82	30	simon111	`always @(posedge usbclk)`
83			`if(ep6_havedata)`
84			`begin`
85			`sloe<=1'h0;`
86			`fifoadr<=2'h2;`
87			`slrd<=1'h0;`
88			`slwr<=1'h1;`
89			last_action<=`EP6_R;
90			`end`
91			`else`
92			`if(ep8_havedata)`
93			`begin`
94			`sloe<=1'h0;`
95			`fifoadr<=2'h3;`
96			`slrd<=1'h0;`
97			`slwr<=1'h1;`
98			last_action<=`EP8_R;
99			`end`
100			`else`
101			`if(ep2_haveroom)`
102			`begin`
103			`// ouput data`
104			`sloe<=1'h1;`
105			`fifoadr<=2'h0;`
106			`slwr<=1'h0;`
107			`slrd<=1'h1;`
108			last_action<=`EP2_W;
109
110			`end`
111			`else`
112			`begin`
113			`sloe<=1'h1;`
114			`fifoadr<=2'h0;`
115			`slwr<=1'h1;`
116			`slrd<=1'h1;`
117			last_action<=`NO_ACT;
118			`end`
119
120			`always @(posedge usbclk)`
121			if(last_action==`EP8_R )
122			`usb_dat_in<=fd;`
123
124			`assign fd=(sloe)?usb_dat_out:16'hzzzz;`
125
126	28	simon111	`////////////////////////////////////////////////////////////////////////////////`
127			`// csa decrypt module`
128			`////////////////////////////////////////////////////////////////////////////////`
129			`decrypt csa_decrypt(`
130	30	simon111	`. clk (usbclk)`
131	28	simon111	`,. rst (rst)`
132			`,. ck (64'h0000000000000000)`
133			`,. key_en (1'h0)`
134			`,. even_odd (1'h0)`
135			`,. en ()`
136			`,. encrypted ()`
137			`,. decrypted ()`
138			`,. invalid ()`
139			`);`
140
141
142			`endmodule`
143

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[/] [csa/] [trunk/] [quartus10/] [csa_fpga.v] - Blame information for rev 30