1 |
5 |
regttycomi |
`timescale 1ns / 1ps
|
2 |
|
|
//////////////////////////////////////////////////////////////////////////////////
|
3 |
|
|
// Company:
|
4 |
|
|
// Engineer:
|
5 |
|
|
//
|
6 |
|
|
// Create Date: 19:53:31 03/10/2009
|
7 |
|
|
// Design Name:
|
8 |
|
|
// Module Name: CheckDNA
|
9 |
|
|
// Project Name:
|
10 |
|
|
// Target Devices:
|
11 |
|
|
// Tool versions:
|
12 |
|
|
// Description:
|
13 |
|
|
//
|
14 |
|
|
// Dependencies:
|
15 |
|
|
//
|
16 |
|
|
// Revision:
|
17 |
|
|
// Revision 0.01 - File Created
|
18 |
|
|
// Additional Comments:
|
19 |
|
|
//
|
20 |
|
|
//////////////////////////////////////////////////////////////////////////////////
|
21 |
|
|
module CheckDNA(
|
22 |
|
|
input clk4,
|
23 |
|
|
input reset,
|
24 |
|
|
input [63:0] DNA_64, // The DNA code
|
25 |
|
|
input dna_valid,
|
26 |
|
|
|
27 |
|
|
input [15:0] ROM_Data, // ROM data
|
28 |
|
|
input IDE_CS, // chip select killer signal
|
29 |
|
|
output reg DNA_ENA, // the enable signal to reduce power consumption
|
30 |
|
|
output reg DNA_REG, // enable output register for faster RAM access
|
31 |
|
|
output reg [9:0] DNA_Addr, // RAM address
|
32 |
|
|
|
33 |
|
|
output dna_pass, // result of check
|
34 |
|
|
output [3:0] KILL // Killing signals
|
35 |
|
|
);
|
36 |
|
|
|
37 |
|
|
// Result of check
|
38 |
|
|
// DNA_FailR[0] = set to 1 if (XOR check sum is not zero) or (DNA address in [1018-1022] does not match with local DNA)
|
39 |
|
|
// DNA_FailR[1] = set to 1 if {DNA address in [1018-1022] not match with local DNA)
|
40 |
|
|
// DNA_FailR[2] = set to 1 if (
|
41 |
|
|
// DNA_FailR[3] = set to 1 if
|
42 |
|
|
// parameter no_of_ran_no = 1021; // for server1104
|
43 |
|
|
parameter no_of_ran_no = 1016; // For Server1108
|
44 |
|
|
|
45 |
|
|
reg [15:0] xor_check; // overall check key of the XOR
|
46 |
|
|
reg [63:0] dna; // local dna code
|
47 |
|
|
reg [9:0] L_Addr; // the addres of the check code
|
48 |
|
|
reg [15:0] check; // the content of the check code
|
49 |
|
|
reg multi_ce; // enable the multiplier signal
|
50 |
|
|
reg [4:0] dna_gen_st; // dna state machine
|
51 |
|
|
reg [3:0] DNA_FailR; // dna failing reigster
|
52 |
|
|
|
53 |
|
|
parameter DcIdle = 5'b00000;
|
54 |
|
|
parameter Dc01 = 5'b00001;
|
55 |
|
|
parameter Dc02 = 5'b00010;
|
56 |
|
|
parameter Dc03 = 5'b00011;
|
57 |
|
|
parameter Dc04 = 5'b00100;
|
58 |
|
|
parameter Dc10 = 5'b00101;
|
59 |
|
|
parameter Dc11 = 5'b00110;
|
60 |
|
|
parameter Dc12 = 5'b00111;
|
61 |
|
|
parameter Dc13 = 5'b01000;
|
62 |
|
|
parameter Dc14 = 5'b01001;
|
63 |
|
|
parameter Dc20 = 5'b01010;
|
64 |
|
|
parameter Dc21 = 5'b01011;
|
65 |
|
|
parameter Dc22 = 5'b01100;
|
66 |
|
|
parameter Dc23 = 5'b01101;
|
67 |
|
|
parameter Dc24 = 5'b01110;
|
68 |
|
|
parameter Dc25 = 5'b01111;
|
69 |
|
|
parameter Dc26 = 5'b10000;
|
70 |
|
|
parameter Dc27 = 5'b10001;
|
71 |
|
|
parameter Dc28 = 5'b10010;
|
72 |
|
|
parameter Dc29 = 5'b10011;
|
73 |
|
|
parameter Dc30 = 5'b10100;
|
74 |
|
|
parameter Dc31 = 5'b10101;
|
75 |
|
|
parameter Dc32 = 5'b10110;
|
76 |
|
|
parameter Dc33 = 5'b10111;
|
77 |
|
|
parameter Dc34 = 5'b11000;
|
78 |
|
|
parameter Dc35 = 5'b11001;
|
79 |
|
|
parameter Dc90 = 5'b11010;
|
80 |
|
|
parameter Dc91 = 5'b11011;
|
81 |
|
|
parameter Dc92 = 5'b11100;
|
82 |
|
|
|
83 |
|
|
reg [15:0] multi_a;
|
84 |
|
|
reg [15:0] multi_b;
|
85 |
|
|
reg [15:0] Simp_XOR; // simple XOR register
|
86 |
|
|
reg FinishCheck; // flip flop to show checking is finished
|
87 |
|
|
wire [15:0] multi_p; // output of register
|
88 |
|
|
wire [15:0] ma; // input feed of multi_a
|
89 |
|
|
wire [15:0] mb; // input feed of multi_b
|
90 |
|
|
wire K_WINDOW; // wire key window
|
91 |
|
|
|
92 |
|
|
///////////////////////////////////////////////////////////////
|
93 |
|
|
|
94 |
|
|
multi_16 inst_multi_16 (
|
95 |
|
|
.ce(multi_ce),
|
96 |
|
|
.clk(clk4),
|
97 |
|
|
.a(multi_a), // Bus [15 : 0]
|
98 |
|
|
.b(multi_b), // Bus [15 : 0]
|
99 |
|
|
.p(multi_p)); // Bus [15 : 0]
|
100 |
|
|
|
101 |
|
|
// Server1104 = algorithm
|
102 |
|
|
//Multi_A = XOR_REG( DNA_64(18,24) + DNA_64(26,28) + DNA_64(30,32) + DNA_64(33,39)),
|
103 |
|
|
// Multi_P(0,6) + Multi_P(8, 10) + Multi_P(6, 8) + Multi_P(10, 16));
|
104 |
|
|
//Multi_B = XOR_REG(ROM_Data(0,16), DNA_64(48,64));
|
105 |
|
|
//assign ma[15:10] = multi_p[15:10] ^ dna[45:40]; // Multi_P(0,6) ^ DNA_64(18,24)
|
106 |
|
|
//assign ma[9:8] = multi_p[7:6] ^ dna[37:36]; // Multi_P(8,10) ^ DNA_64(26,28)
|
107 |
|
|
//assign ma[7:6] = multi_p[9:8] ^ dna[33:32]; // Multi_P(6,8) ^ DNA_64(30,32)
|
108 |
|
|
//assign ma[5:0] = multi_p[5:0] ^ dna[30:25]; // Multi_P(10,16) ^ DNA_64(33,39)
|
109 |
|
|
//assign mb[15:0] = ROM_Data[15:0] ^ dna[15:0]; // ROM_Data(0,16) ^ DNA_64(48,64)
|
110 |
|
|
|
111 |
|
|
// Server1108 = algorithm
|
112 |
|
|
//Multi_A = XOR_REG( DNA_64(16,22) + DNA_64(26,28) + DNA_64(30,32) + DNA_64(33,39)),
|
113 |
|
|
// Multi_P(0,6) + Multi_P(8, 10) + Multi_P(6, 8) + Multi_P(10, 16));
|
114 |
|
|
//Multi_B = XOR_REG(ROM_Data(0,16), DNA_64(44,60));
|
115 |
|
|
assign ma[15:10] = multi_p[15:10] ^ dna[47:42]; // Multi_P(0,6) ^ DNA_64(16,22)
|
116 |
|
|
assign ma[9:8] = multi_p[7:6] ^ dna[37:36]; // Multi_P(8,10) ^ DNA_64(26,28)
|
117 |
|
|
assign ma[7:6] = multi_p[9:8] ^ dna[33:32]; // Multi_P(6,8) ^ DNA_64(30,32)
|
118 |
|
|
assign ma[5:0] = multi_p[5:0] ^ dna[30:25]; // Multi_P(10,16) ^ DNA_64(33,39)
|
119 |
|
|
assign mb[15:0] = ROM_Data[15:0] ^ dna[20:4]; // ROM_Data(0,16) ^ DNA_64(44,60)
|
120 |
|
|
|
121 |
|
|
/////////////////////// Killing signals ////////////////////
|
122 |
|
|
assign KILL[0] = DNA_FailR[0]; // Fail register to output the signal
|
123 |
|
|
assign KILL[1] = ~DNA_FailR[0] & DNA_FailR[1] & K_WINDOW & Simp_XOR[2]; // If someone modify the Fail 0, then we create new fail for them
|
124 |
|
|
assign KILL[2] = ~DNA_FailR[0] & ~DNA_FailR[1] & DNA_FailR[2] & K_WINDOW & ~Simp_XOR[2];
|
125 |
|
|
assign KILL[3] = ~DNA_FailR[0] & ~DNA_FailR[1] & DNA_FailR[3] & K_WINDOW & Simp_XOR[2];
|
126 |
|
|
assign K_WINDOW = Simp_XOR[9] & Simp_XOR[8] & ~Simp_XOR[7] & Simp_XOR[6] & ~Simp_XOR[5] & ~Simp_XOR[3];
|
127 |
|
|
assign dna_pass = FinishCheck & ~DNA_FailR[3] & ~DNA_FailR[2] & ~DNA_FailR[1] & ~DNA_FailR[0];
|
128 |
|
|
|
129 |
|
|
always @(posedge clk4) begin
|
130 |
|
|
if(reset) begin
|
131 |
|
|
DNA_Addr <= 10'b00_0000_0000; // address of ROM_Data
|
132 |
|
|
L_Addr <= 10'b00_0000_0000; // address of check_code
|
133 |
|
|
xor_check <= 16'b0000_0000_0000_0000; // the XOR A bus check code
|
134 |
|
|
multi_a <= 16'b0000_0000_0000_0000; // the two multipliers check code
|
135 |
|
|
multi_b <= 16'b0000_0000_0000_0000; // the two multipliers bus check code
|
136 |
|
|
Simp_XOR <= 16'b0000_0000_0000_0000; // simple XOR register
|
137 |
|
|
DNA_FailR <= 4'b0000; // clear the fail register
|
138 |
|
|
FinishCheck <= 1'b0; // clear the check phase
|
139 |
|
|
DNA_ENA <= 1'b0;
|
140 |
|
|
DNA_REG <= 1'b0;
|
141 |
|
|
multi_ce <= 1'b0;
|
142 |
|
|
dna_gen_st <= DcIdle; // start in the idle state
|
143 |
|
|
end else begin
|
144 |
|
|
case(dna_gen_st)
|
145 |
|
|
//// ===== state 0, wait until dna code is valid ============
|
146 |
|
|
//// Formulate a dna_check_key to combat zero code attack
|
147 |
|
|
DcIdle : begin
|
148 |
|
|
if(dna_valid == 1'b1) begin
|
149 |
|
|
dna_gen_st <= Dc01;
|
150 |
|
|
end
|
151 |
|
|
end
|
152 |
|
|
Dc01 : begin
|
153 |
|
|
DNA_ENA <= 1'b1; // enable reading the ROM
|
154 |
|
|
multi_ce <= 1'b1; // flush the multiplier with 0s
|
155 |
|
|
dna <= DNA_64; // clock in the main register
|
156 |
|
|
dna_gen_st <= Dc02;
|
157 |
|
|
end
|
158 |
|
|
Dc02 : begin
|
159 |
|
|
DNA_ENA <= 1'b0; // disable reading the ROM
|
160 |
|
|
DNA_REG <= 1'b1; // fetch first ROM data to bus
|
161 |
|
|
dna_gen_st <= Dc03;
|
162 |
|
|
end
|
163 |
|
|
Dc03 : begin
|
164 |
|
|
DNA_REG <= 1'b0;
|
165 |
|
|
dna_gen_st <= Dc04;
|
166 |
|
|
end
|
167 |
|
|
Dc04 : begin
|
168 |
|
|
multi_ce <= 1'b0; // multiplier completely flushed
|
169 |
|
|
multi_a[15:0] <= ma[15:0];
|
170 |
|
|
multi_b[15:0] <= mb[15:0];
|
171 |
|
|
L_Addr[9] <= ~mb[10]; // mult address is stable now
|
172 |
|
|
L_Addr[8:0] <= mb[10:2]; // check address is between 256-767
|
173 |
|
|
dna_gen_st <= Dc10; // go to the main loop
|
174 |
|
|
end
|
175 |
|
|
//// ====== Check on the data block ===========
|
176 |
|
|
Dc10: begin
|
177 |
|
|
DNA_REG <= 1'b0;
|
178 |
|
|
dna_gen_st <= Dc11; // next state
|
179 |
|
|
end
|
180 |
|
|
Dc11: begin
|
181 |
|
|
multi_ce <= 1'b1;
|
182 |
|
|
multi_a[15:0] <= ma[15:0]; // activate the multipliers
|
183 |
|
|
multi_b[15:0] <= mb[15:0];
|
184 |
|
|
dna_gen_st <= Dc12; // next state
|
185 |
|
|
end
|
186 |
|
|
Dc12: begin
|
187 |
|
|
dna[63:1] <= dna[62:0];
|
188 |
|
|
dna[0] <= dna[63] ^ ROM_Data[1]; // bitwise rotate the data
|
189 |
|
|
DNA_ENA <= 1'b0; // save power for the ROM
|
190 |
|
|
if (DNA_Addr == L_Addr) check <= multi_a; // store up the value of check instance
|
191 |
|
|
DNA_Addr <= DNA_Addr + 1; // proceed to next address
|
192 |
|
|
Simp_XOR[15:0] <= Simp_XOR[15:0] ^ ROM_Data[15:0]; // mask the registers
|
193 |
|
|
xor_check <= xor_check ^ multi_b; // the xor algorithm is base on dna XOR ROM_Data
|
194 |
|
|
dna_gen_st <= Dc13;
|
195 |
|
|
end
|
196 |
|
|
Dc13: begin
|
197 |
|
|
DNA_ENA <= 1'b1; // enable back the ROM
|
198 |
|
|
dna_gen_st <= Dc14;
|
199 |
|
|
end
|
200 |
|
|
Dc14: begin
|
201 |
|
|
DNA_ENA <= 1'b0; // disable ROM access
|
202 |
|
|
DNA_REG <= 1'b1; // enable back the ROM and reg
|
203 |
|
|
if (DNA_Addr == no_of_ran_no) begin
|
204 |
|
|
DNA_Addr <= DNA_Addr + 1; // advance the address
|
205 |
|
|
dna_gen_st <= Dc20; // go to the result phase
|
206 |
|
|
end else begin
|
207 |
|
|
dna_gen_st <= Dc10; // loop back for new computation
|
208 |
|
|
end
|
209 |
|
|
end
|
210 |
|
|
//// ======================================================
|
211 |
|
|
Dc20 : begin // DNA_Addr = 1016
|
212 |
|
|
multi_ce <= 1'b0; // save some power
|
213 |
|
|
DNA_REG <= 1'b0; // lock down the reg
|
214 |
|
|
DNA_ENA <= 1'b1; // clock out the data to register side
|
215 |
|
|
dna_gen_st <= Dc21;
|
216 |
|
|
end
|
217 |
|
|
Dc21 : begin
|
218 |
|
|
Simp_XOR[15:0] <= Simp_XOR[15:0] ^ ROM_Data[15:0]; // mask the registers
|
219 |
|
|
if (multi_a != ROM_Data) begin
|
220 |
|
|
DNA_FailR[3] <= 1'b1; // 3rd level fail
|
221 |
|
|
end
|
222 |
|
|
DNA_REG <= 1'b1; // clock out the data to compare
|
223 |
|
|
DNA_ENA <= 1'b0; // lock down the RAM area
|
224 |
|
|
DNA_Addr <= DNA_Addr+1; // pipe the new address 1017 to RAM
|
225 |
|
|
dna_gen_st <= Dc22;
|
226 |
|
|
end
|
227 |
|
|
Dc22 : begin // DNA_Addr = 1017
|
228 |
|
|
DNA_REG <= 1'b0; // lock down the reg
|
229 |
|
|
DNA_ENA <= 1'b1; // clock out the data to register side
|
230 |
|
|
dna_gen_st <= Dc23;
|
231 |
|
|
end
|
232 |
|
|
Dc23 : begin
|
233 |
|
|
Simp_XOR[15:0] <= Simp_XOR[15:0] ^ ROM_Data[15:0]; // mask the registers
|
234 |
|
|
if (xor_check != ROM_Data) begin
|
235 |
|
|
DNA_FailR[2] <= 1'b1; // 2nd level fail
|
236 |
|
|
end
|
237 |
|
|
DNA_REG <= 1'b1; // clock out the data to compare
|
238 |
|
|
DNA_ENA <= 1'b0; // lock down the RAM area
|
239 |
|
|
DNA_Addr <= DNA_Addr+1; // pipe the new address to RAM
|
240 |
|
|
dna_gen_st <= Dc24;
|
241 |
|
|
end
|
242 |
|
|
////////
|
243 |
|
|
Dc24 : begin // DNA_Addr = 1018
|
244 |
|
|
DNA_REG <= 1'b0; // lock down the reg
|
245 |
|
|
DNA_ENA <= 1'b1;
|
246 |
|
|
dna_gen_st <= Dc25;
|
247 |
|
|
end
|
248 |
|
|
Dc25 : begin // DNA_Addr = 1018
|
249 |
|
|
Simp_XOR[15:0] <= Simp_XOR[15:0] ^ ROM_Data[15:0]; // mask the registers
|
250 |
|
|
if (check != ROM_Data) begin
|
251 |
|
|
DNA_FailR[1] <= 1'b1; // set the general fail
|
252 |
|
|
end
|
253 |
|
|
DNA_REG <= 1'b1; // clock out the data to compare
|
254 |
|
|
DNA_ENA <= 1'b0; // lock down the RAM area
|
255 |
|
|
DNA_Addr <= DNA_Addr+1; // pipe the new address to RAM
|
256 |
|
|
dna_gen_st <= Dc26;
|
257 |
|
|
end
|
258 |
|
|
//////////
|
259 |
|
|
Dc26 : begin // DNA_Addr = 1019
|
260 |
|
|
DNA_REG <= 1'b0; // lock down the reg
|
261 |
|
|
DNA_ENA <= 1'b1;
|
262 |
|
|
dna_gen_st <= Dc27;
|
263 |
|
|
end
|
264 |
|
|
Dc27 : begin // DNA_Addr = 1019
|
265 |
|
|
Simp_XOR[15:0] <= Simp_XOR[15:0] ^ ROM_Data[15:0]; // mask the registers
|
266 |
|
|
if (DNA_64[63:48] != ROM_Data[15:0]) begin
|
267 |
|
|
DNA_FailR[0] <= 1'b1;
|
268 |
|
|
end
|
269 |
|
|
DNA_REG <= 1'b1; // clock out the data to compare
|
270 |
|
|
DNA_ENA <= 1'b0; // lock down the RAM area
|
271 |
|
|
DNA_Addr <= DNA_Addr+1; // pipe the new address to RAM
|
272 |
|
|
dna_gen_st <= Dc28;
|
273 |
|
|
end
|
274 |
|
|
//////////
|
275 |
|
|
Dc28 : begin // DNA_Addr = 1020
|
276 |
|
|
DNA_REG <= 1'b0; // lock down the reg
|
277 |
|
|
DNA_ENA <= 1'b1;
|
278 |
|
|
dna_gen_st <= Dc29;
|
279 |
|
|
end
|
280 |
|
|
Dc29 : begin // DNA_Addr = 1020
|
281 |
|
|
Simp_XOR[15:0] <= Simp_XOR[15:0] ^ ROM_Data[15:0]; // mask the registers
|
282 |
|
|
if (DNA_64[47:32] != ROM_Data[15:0]) begin
|
283 |
|
|
DNA_FailR[0] <= 1'b1;
|
284 |
|
|
end
|
285 |
|
|
DNA_REG <= 1'b1; // clock out the data to compare
|
286 |
|
|
DNA_ENA <= 1'b0; // lock down the RAM area
|
287 |
|
|
DNA_Addr <= DNA_Addr+1; // pipe the new address to RAM
|
288 |
|
|
dna_gen_st <= Dc30;
|
289 |
|
|
end
|
290 |
|
|
//////////
|
291 |
|
|
Dc30 : begin // DNA_Addr = 1021
|
292 |
|
|
DNA_REG <= 1'b0; // lock down the reg
|
293 |
|
|
DNA_ENA <= 1'b1;
|
294 |
|
|
dna_gen_st <= Dc31;
|
295 |
|
|
end
|
296 |
|
|
Dc31 : begin // DNA_Addr = 1021
|
297 |
|
|
Simp_XOR[15:0] <= Simp_XOR[15:0] ^ ROM_Data[15:0]; // mask the registers
|
298 |
|
|
if (DNA_64[31:16] != ROM_Data[15:0]) begin
|
299 |
|
|
DNA_FailR[0] <= 1'b1;
|
300 |
|
|
end
|
301 |
|
|
DNA_REG <= 1'b1; // clock out the data to compare
|
302 |
|
|
DNA_ENA <= 1'b0; // lock down the RAM area
|
303 |
|
|
DNA_Addr <= DNA_Addr+1; // pipe the new address to RAM
|
304 |
|
|
dna_gen_st <= Dc32;
|
305 |
|
|
end
|
306 |
|
|
//////////
|
307 |
|
|
Dc32 : begin // DNA_Addr = 1022
|
308 |
|
|
DNA_REG <= 1'b0; // lock down the reg
|
309 |
|
|
DNA_ENA <= 1'b1; // read from ram
|
310 |
|
|
dna_gen_st <= Dc33;
|
311 |
|
|
end
|
312 |
|
|
Dc33 : begin // DNA_Addr = 1022
|
313 |
|
|
Simp_XOR[15:0] <= Simp_XOR[15:0] ^ ROM_Data[15:0]; // mask the registers
|
314 |
|
|
if (DNA_64[15:0] != ROM_Data[15:0]) begin
|
315 |
|
|
DNA_FailR[0] <= 1'b1;
|
316 |
|
|
end
|
317 |
|
|
DNA_REG <= 1'b1; // clock out the data to compare
|
318 |
|
|
DNA_ENA <= 1'b0; // lock down the RAM area
|
319 |
|
|
// DNA_Addr <= DNA_Addr+1; // pipe the new address to RAM
|
320 |
|
|
dna_gen_st <= Dc34;
|
321 |
|
|
end
|
322 |
|
|
//////////
|
323 |
|
|
Dc34 : begin // DNA_Addr = 1023
|
324 |
|
|
DNA_REG <= 1'b0; // lock down the reg
|
325 |
|
|
// DNA_ENA <= 1'b1;
|
326 |
|
|
dna_gen_st <= Dc35;
|
327 |
|
|
end
|
328 |
|
|
Dc35 : begin // DNA_Addr = 1023
|
329 |
|
|
if (Simp_XOR[15:0] != ROM_Data[15:0]) begin
|
330 |
|
|
DNA_FailR[0] <= 1'b1;
|
331 |
|
|
end
|
332 |
|
|
// DNA_REG <= 1'b1; // clock out the data to compare
|
333 |
|
|
// DNA_ENA <= 1'b0; // lock down the RAM area
|
334 |
|
|
// DNA_Addr <= DNA_Addr+1; // pipe the new address to RAM
|
335 |
|
|
FinishCheck <= 1'b1; // exit the check phase
|
336 |
|
|
dna_gen_st <= Dc90;
|
337 |
|
|
end
|
338 |
|
|
///// ============= result found loop here forever
|
339 |
|
|
Dc90: begin
|
340 |
|
|
if (IDE_CS == 1'b0) begin
|
341 |
|
|
dna_gen_st <= Dc91;
|
342 |
|
|
end else begin
|
343 |
|
|
dna_gen_st <= Dc90; // loop here if CS is 1
|
344 |
|
|
end
|
345 |
|
|
end
|
346 |
|
|
//////
|
347 |
|
|
Dc91: begin
|
348 |
|
|
Simp_XOR <= Simp_XOR + 1; // increment the Simp_XOR to generate the internal kill signal
|
349 |
|
|
dna_gen_st <= Dc92;
|
350 |
|
|
end
|
351 |
|
|
//////
|
352 |
|
|
Dc92: begin
|
353 |
|
|
if (IDE_CS == 1'b1) begin
|
354 |
|
|
dna_gen_st <= Dc90; // if 1 goto next state
|
355 |
|
|
end else begin
|
356 |
|
|
dna_gen_st <= Dc92; // loop here if CS is 0
|
357 |
|
|
end
|
358 |
|
|
end
|
359 |
|
|
|
360 |
|
|
//// ===================================
|
361 |
|
|
default : begin
|
362 |
|
|
dna_gen_st <= DcIdle; // loop back to idle
|
363 |
|
|
end
|
364 |
|
|
//// =================================
|
365 |
|
|
endcase
|
366 |
|
|
end /// reset
|
367 |
|
|
end //// clock
|
368 |
|
|
endmodule
|