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john_fpga |
---------------------------------------------------------------------
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-- File : Buttons_VHDL.vhd
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-- Projekt : Prj_12_DDR2
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-- Zweck : Buttons und Schalter entprellen
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-- Datum : 19.08.2011
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-- Version : 2.0
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-- Plattform : XILINX Spartan-3A
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-- FPGA : XC3S700A-FGG484
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-- Sprache : VHDL
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-- ISE : ISE-Design-Suite V:13.1
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-- Autor : UB
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-- Mail : Becker_U(at)gmx.de
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---------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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--------------------------------------------
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-- Beschreibung :
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--
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-- hier werden die Buttons und Schalter
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-- mit dem Clock syncronisiert
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--
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-- weil die Taster prellen
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-- werden sie mit einer Verzögerung eingelesen
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-- sonst kommt es zu anzeigefehlern
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--
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-- damit die Read/Write Funktionen
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-- bei gedruecktem Button nicht
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-- staendig aufgerufen werden,
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-- wird aus allen 4 Buttons
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-- ein OnClick-Eregnis gemacht
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--------------------------------------------
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entity Buttons_VHDL is
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--------------------------------------------
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-- Port Deklerationen
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--------------------------------------------
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port (
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clk_in : in std_logic;
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button_in : in std_logic_vector(3 downto 0);
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switch_in : in std_logic_vector(3 downto 0);
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debounce_out : out std_logic_vector(7 downto 0);
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risingedge_out : out std_logic_vector(3 downto 0)
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);
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end Buttons_VHDL;
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architecture Verhalten of Buttons_VHDL is
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--------------------------------------------
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-- Interne Signale
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--------------------------------------------
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signal v_debounce : std_logic_vector(7 downto 0) := (others => '0');
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signal v_btn_old : std_logic_vector(3 downto 0):= (others => '0');
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signal v_btn_tic : std_logic_vector(3 downto 0):= (others => '0');
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-- verzoegerung für die tasten, weil sie prellen
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constant BUTTON_SLEEP : integer := 6650000; -- Zeit = 50ms bei 133MHz Quarz
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signal v_counter : natural range 0 to BUTTON_SLEEP := BUTTON_SLEEP;
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begin
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-----------------------------------------
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-- Einclocken von Asyncronen Signalen
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-----------------------------------------
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P_ASYNC : process(clk_in)
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begin
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if falling_edge(clk_in) then
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if v_counter = 0 then
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-- wenn Verzögerungszeit um, die zustände der
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-- buttons und schalter übergeben
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v_counter <= BUTTON_SLEEP;
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v_debounce(3 downto 0) <= button_in(3 downto 0);
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v_debounce(7 downto 4) <= switch_in(3 downto 0);
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else
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v_counter <= v_counter -1;
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end if;
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end if;
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end process P_ASYNC;
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-- übergabe der Signale------------------
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debounce_out <= v_debounce;
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-----------------------------------------
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-- Aus den Tastern jeweils ein
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-- einzelnes 1Clock langes Signal machen,
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-- bis der Taser wieder verlassen ist
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-- damit die Funktionen (+/-, read,write)
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-- nur einmal ausgeführt werden
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-----------------------------------------
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P_Buttons : process(clk_in)
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begin
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if falling_edge(clk_in) then
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-- TIC merker zurücksetzen
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v_btn_tic(3 downto 0) <= "0000";
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-- button east-------------------------------
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if v_debounce(0)='1' and v_btn_old(0)='0' then
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v_btn_old(0) <= '1';
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v_btn_tic(0) <= '1';
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elsif v_debounce(0)='0' and v_btn_old(0)='1' then
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v_btn_old(0) <= '0';
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end if;
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-- button north-----------------------------
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if v_debounce(1)='1' and v_btn_old(1)='0' then
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v_btn_old(1) <= '1';
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v_btn_tic(1) <= '1';
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elsif v_debounce(1)='0' and v_btn_old(1)='1' then
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v_btn_old(1) <= '0';
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end if;
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-- button south-----------------------------
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if v_debounce(2)='1' and v_btn_old(2)='0' then
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v_btn_old(2) <= '1';
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v_btn_tic(2) <= '1';
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elsif v_debounce(2)='0' and v_btn_old(2)='1' then
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v_btn_old(2) <= '0';
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end if;
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-- button west------------------------------
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if v_debounce(3)='1' and v_btn_old(3)='0' then
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v_btn_old(3) <= '1';
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v_btn_tic(3) <= '1';
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elsif v_debounce(3)='0' and v_btn_old(3)='1' then
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v_btn_old(3) <= '0';
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end if;
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end if;
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end process P_Buttons;
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-- übergabe der Signale------------------
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risingedge_out <= v_btn_tic;
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end Verhalten;
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