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john_fpga |
---------------------------------------------------------------------
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-- File : Top_Modul_VHDL.vhd
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-- Projekt : Prj_12_DDR2
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-- Zweck : DDR2-SDRAM am Spartan-3A Board
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-- DDR2-RAM : MT47H32M16 (64 MByte)
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-- Datum : 19.08.2011
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-- Version : 7.0
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-- Plattform : XILINX Spartan-3A
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-- FPGA : XC3S700A-FGG484
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-- Sprache : VHDL
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-- ISE : ISE-Design-Suite V:13.1
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-- IP-Core : MIG V:3.6.1
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-- Autor : UB
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-- Mail : Becker_U(at)gmx.de
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---------------------------------------------------------------------
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--
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-- Bitte auch die Hinweise in der "DDR2_liesmich.txt" beachten
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--
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-- please have a look at the "DDR2_readme.txt"
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-- and sorry for my bad english :-)
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--
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---------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity Top_Modul_VHDL is
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--------------------------------------------
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-- Port Deklerationen
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--------------------------------------------
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port(
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CLK_AUX_IN : in std_logic;
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LED_OUT : out std_logic_vector(7 downto 0);
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LED_YELLOW_OUT : out std_logic;
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SW_IN : in std_logic_vector(3 downto 0);
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BTN_IN : in std_logic_vector(3 downto 0);
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----------------------------------------------------
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-- DDR2 SDRAM-Port-Pins
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----------------------------------------------------
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cntrl0_ddr2_a : out std_logic_vector(12 downto 0) := (others => '0');
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cntrl0_ddr2_ba : out std_logic_vector(1 downto 0) := (others => '0');
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cntrl0_ddr2_ck : out std_logic_vector(0 downto 0) := (others => '0');
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cntrl0_ddr2_ck_n : out std_logic_vector(0 downto 0) := (others => '0');
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cntrl0_ddr2_cke : out std_logic := '0';
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cntrl0_ddr2_cs_n : out std_logic := '0';
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cntrl0_ddr2_ras_n : out std_logic := '0';
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cntrl0_ddr2_cas_n : out std_logic := '0';
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cntrl0_ddr2_we_n : out std_logic := '0';
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cntrl0_ddr2_odt : out std_logic := '0';
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cntrl0_ddr2_dm : out std_logic_vector(1 downto 0) := (others => '0');
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cntrl0_ddr2_dqs_n : inout std_logic_vector(1 downto 0) := (others => '0');
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cntrl0_ddr2_dqs : inout std_logic_vector(1 downto 0) := (others => '0');
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cntrl0_ddr2_dq : inout std_logic_vector(15 downto 0) := (others => '0');
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cntrl0_rst_dqs_div_in : in std_logic;
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cntrl0_rst_dqs_div_out : out std_logic
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----------------------------------------------------
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);
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end Top_Modul_VHDL;
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architecture Verhalten of Top_Modul_VHDL is
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--------------------------------------------
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-- Interne Signale
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--------------------------------------------
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signal v_reset_n : std_logic;
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signal v_reset_p : std_logic;
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signal v_debounce : std_logic_vector(7 downto 0) := (others => '0');
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signal v_risingedge : std_logic_vector(3 downto 0) := (others => '0');
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-- DDR2 SDRAM-Leitungen -----------------------------------------
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signal clk_tb : std_logic;
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signal clk90_tb : std_logic;
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signal burst_done : std_logic;
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signal user_command_register : std_logic_vector(2 downto 0) := (others => '0');
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signal user_data_mask : std_logic_vector(3 downto 0):= (others => '0');
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signal user_input_data : std_logic_vector(31 downto 0);
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signal user_input_address : std_logic_vector(24 downto 0);
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signal v_init_done : std_logic;
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signal ar_done : std_logic;
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signal auto_ref_req : std_logic;
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signal user_cmd_ack : std_logic;
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signal user_data_valid : std_logic;
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signal user_output_data : std_logic_vector(31 downto 0);
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---------------------------------------------------------------------
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--------------------------------------------
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-- Einbinden einer Componente
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-- Clock_VHDL : für die Clockerzeugung
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--------------------------------------------
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COMPONENT Clock_VHDL is
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PORT (
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clk_in_133MHz : in std_logic;
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clk_out_1Hz : out std_logic
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);
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END COMPONENT Clock_VHDL;
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--------------------------------------------
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-- Einbinden einer Componente
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-- Buttons_VHDL : für die Buttons und Schalter
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--------------------------------------------
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COMPONENT Buttons_VHDL is
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PORT (
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clk_in : in std_logic;
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button_in : in std_logic_vector(3 downto 0);
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switch_in : in std_logic_vector(3 downto 0);
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debounce_out : out std_logic_vector(7 downto 0);
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risingedge_out : out std_logic_vector(3 downto 0)
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);
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END COMPONENT Buttons_VHDL;
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--------------------------------------------
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-- Einbinden einer Componente
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-- VHDL um das DDR2 zu steuern
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--------------------------------------------
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COMPONENT DDR2_Control_VHDL is
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PORT (
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reset_in : in std_logic;
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clk_in : in std_logic;
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clk90_in : in std_logic;
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init_done : in std_logic;
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command_register : out std_logic_vector(2 downto 0);
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input_adress : out std_logic_vector(24 downto 0);
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input_data : out std_logic_vector(31 downto 0);
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output_data : in std_logic_vector(31 downto 0);
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cmd_ack : in std_logic;
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data_valid : in std_logic;
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burst_done : out std_logic;
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auto_ref_req : in std_logic;
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debounce_in : in std_logic_vector(7 downto 0);
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risingedge_in : in std_logic_vector(3 downto 0);
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data_out : out std_logic_vector(7 downto 0)
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);
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END COMPONENT DDR2_Control_VHDL;
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--------------------------------------------
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-- Einbinden einer Componente
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-- DDR2_RAM_Modul (vom MIG generiert)
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--------------------------------------------
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COMPONENT DDR2_Ram_Core is
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PORT (
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cntrl0_ddr2_dq : inout std_logic_vector(15 downto 0);
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cntrl0_ddr2_a : out std_logic_vector(12 downto 0);
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cntrl0_ddr2_ba : out std_logic_vector(1 downto 0);
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cntrl0_ddr2_cke : out std_logic;
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cntrl0_ddr2_cs_n : out std_logic;
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cntrl0_ddr2_ras_n : out std_logic;
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cntrl0_ddr2_cas_n : out std_logic;
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cntrl0_ddr2_we_n : out std_logic;
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cntrl0_ddr2_odt : out std_logic;
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cntrl0_ddr2_dm : out std_logic_vector(1 downto 0);
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cntrl0_rst_dqs_div_in : in std_logic;
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cntrl0_rst_dqs_div_out : out std_logic;
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sys_clk_in : in std_logic;
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reset_in_n : in std_logic;
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cntrl0_burst_done : in std_logic;
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cntrl0_init_done : out std_logic;
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cntrl0_ar_done : out std_logic;
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cntrl0_user_data_valid : out std_logic;
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cntrl0_auto_ref_req : out std_logic;
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cntrl0_user_cmd_ack : out std_logic;
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cntrl0_user_command_register : in std_logic_vector(2 downto 0);
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cntrl0_clk_tb : out std_logic;
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cntrl0_clk90_tb : out std_logic;
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cntrl0_sys_rst_tb : out std_logic;
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cntrl0_sys_rst90_tb : out std_logic;
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cntrl0_sys_rst180_tb : out std_logic;
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cntrl0_user_output_data : out std_logic_vector(31 downto 0);
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cntrl0_user_input_data : in std_logic_vector(31 downto 0);
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cntrl0_user_data_mask : in std_logic_vector(3 downto 0);
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cntrl0_user_input_address : in std_logic_vector(24 downto 0);
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cntrl0_ddr2_dqs : inout std_logic_vector(1 downto 0);
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cntrl0_ddr2_dqs_n : inout std_logic_vector(1 downto 0);
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cntrl0_ddr2_ck : out std_logic_vector(0 downto 0);
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cntrl0_ddr2_ck_n : out std_logic_vector(0 downto 0)
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);
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END COMPONENT DDR2_Ram_Core;
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begin
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--------------------------------------------------
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-- Instantz einer Componente erzeugen und verbinden
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-- Clock_VHDL : für die Clockerzeugung
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--------------------------------------------------
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INST_Clock_VHDL : Clock_VHDL
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PORT MAP (
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clk_in_133MHz => clk_tb,
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clk_out_1Hz => LED_YELLOW_OUT
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);
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--------------------------------------------------
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-- Instantz einer Componente erzeugen und verbinden
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-- VHDL um die Buttons/Schalter zu bearbeiten
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--------------------------------------------------
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INST_Buttons_VHDL : Buttons_VHDL
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PORT MAP (
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clk_in => clk_tb,
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button_in => BTN_IN,
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switch_in => SW_IN,
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debounce_out => v_debounce,
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risingedge_out => v_risingedge
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);
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--------------------------------------------------
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-- Instantz einer Componente erzeugen und verbinden
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-- VHDL um das DDR2 zu steuern
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--------------------------------------------------
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INST_DDR2_Control_VHDL : DDR2_Control_VHDL
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PORT MAP (
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reset_in => v_reset_p,
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clk_in => clk_tb,
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clk90_in => clk90_tb,
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init_done => v_init_done,
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command_register => user_command_register,
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input_adress => user_input_address,
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input_data => user_input_data,
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output_data => user_output_data,
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cmd_ack => user_cmd_ack,
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data_valid => user_data_valid,
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burst_done => burst_done,
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auto_ref_req => auto_ref_req,
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debounce_in => v_debounce,
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risingedge_in => v_risingedge,
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data_out => LED_OUT
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);
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--------------------------------------------------
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-- Instantz einer Componente erzeugen und verbinden
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-- DDR2_RAM_Modul (vom MIG generiert)
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--------------------------------------------------
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INST_DDR2_RAM_CORE : DDR2_Ram_Core
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PORT MAP (
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sys_clk_in => CLK_AUX_IN,
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reset_in_n => v_reset_n,
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cntrl0_burst_done => burst_done,
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cntrl0_user_command_register => user_command_register,
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cntrl0_user_data_mask => user_data_mask,
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cntrl0_user_input_data => user_input_data,
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cntrl0_user_input_address => user_input_address,
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cntrl0_init_done => v_init_done,
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cntrl0_ar_done => ar_done,
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cntrl0_auto_ref_req => auto_ref_req,
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cntrl0_user_cmd_ack => user_cmd_ack,
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cntrl0_clk_tb => clk_tb,
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cntrl0_clk90_tb => clk90_tb,
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cntrl0_sys_rst_tb => open,
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cntrl0_sys_rst90_tb => open,
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cntrl0_sys_rst180_tb => open,
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cntrl0_user_data_valid => user_data_valid,
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cntrl0_user_output_data => user_output_data,
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cntrl0_ddr2_ras_n => cntrl0_ddr2_ras_n,
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cntrl0_ddr2_cas_n => cntrl0_ddr2_cas_n,
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cntrl0_ddr2_we_n => cntrl0_ddr2_we_n,
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cntrl0_ddr2_cs_n => cntrl0_ddr2_cs_n,
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cntrl0_ddr2_cke => cntrl0_ddr2_cke,
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cntrl0_ddr2_dm => cntrl0_ddr2_dm,
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cntrl0_ddr2_ba => cntrl0_ddr2_ba,
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cntrl0_ddr2_a => cntrl0_ddr2_a,
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cntrl0_ddr2_ck => cntrl0_ddr2_ck,
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cntrl0_ddr2_ck_n => cntrl0_ddr2_ck_n,
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cntrl0_ddr2_dqs => cntrl0_ddr2_dqs,
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cntrl0_ddr2_dqs_n => cntrl0_ddr2_dqs_n,
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cntrl0_ddr2_dq => cntrl0_ddr2_dq,
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cntrl0_ddr2_odt => cntrl0_ddr2_odt,
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cntrl0_rst_dqs_div_in => cntrl0_rst_dqs_div_in,
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cntrl0_rst_dqs_div_out => cntrl0_rst_dqs_div_out
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);
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-----------------------------------------
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-- Reset-Signal aus einem Schalter generieren
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-----------------------------------------
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v_reset_p <= SW_IN(0);
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v_reset_n <= not v_reset_p;
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end Verhalten;
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