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[/] [ddr2_sdram/] [trunk/] [Top_Modul_VHDL_bitgen.xwbt] - Blame information for rev 2
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john_fpga |
INTSTYLE=ise
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INFILE=F:\Data_Temp_Ordner\Xilinx\Projekte\Test_Prj_VHDL\Prj_12_DDR2\Prj_12_DDR2\Top_Modul_VHDL.ncd
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OUTFILE=F:\Data_Temp_Ordner\Xilinx\Projekte\Test_Prj_VHDL\Prj_12_DDR2\Prj_12_DDR2\Top_Modul_VHDL.bit
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FAMILY=Spartan3A and Spartan3AN
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PART=xc3s700a-4fg484
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WORKINGDIR=F:\Data_Temp_Ordner\Xilinx\Projekte\Test_Prj_VHDL\Prj_12_DDR2\Prj_12_DDR2
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LICENSE=WebPack
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USER_INFO=205456775_0_0_536
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