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john_fpga |
--*****************************************************************************
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-- DISCLAIMER OF LIABILITY
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-- This file contains proprietary and confidential information of
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-- from Xilinx, and may be used, copied and/or disclosed only
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--
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-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
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-- applications"). Customer assumes the sole risk and liability
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-- of any use of Xilinx products in critical applications,
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-- subject only to applicable laws and regulations governing
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-- limitations on product liability.
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--
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-- Copyright 2005, 2006, 2007, 2008 Xilinx, Inc.
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-- All rights reserved.
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--
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-- This disclaimer and copyright notice must be retained as part
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-- of this file at all times.
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--*****************************************************************************
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-- ____ ____
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-- / /\/ /
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-- /___/ \ / Vendor : Xilinx
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-- \ \ \/ Version : 3.6.1
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-- \ \ Application : MIG
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-- / / Filename : %module_name.vhd
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-- /___/ /\ Date Last Modified : $Date: 2010/11/26 18:25:42 $
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-- \ \ / \ Date Created : Mon May 2 2005
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-- \___\/\___\
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-- Device : Spartan-3/3A/3A-DSP
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-- Design Name : DDR2 SDRAM
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-- Purpose : This module has the instantiations infrastructure_top and
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-- main modules.
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--*****************************************************************************
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library ieee;
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library UNISIM;
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use ieee.std_logic_1164.all;
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use UNISIM.VCOMPONENTS.all;
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entity DDR2_Ram_Core is
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port (
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cntrl0_ddr2_dq : inout std_logic_vector(15 downto 0);
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cntrl0_ddr2_a : out std_logic_vector(12 downto 0);
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cntrl0_ddr2_ba : out std_logic_vector(1 downto 0);
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cntrl0_ddr2_cke : out std_logic;
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cntrl0_ddr2_cs_n : out std_logic;
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cntrl0_ddr2_ras_n : out std_logic;
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cntrl0_ddr2_cas_n : out std_logic;
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cntrl0_ddr2_we_n : out std_logic;
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cntrl0_ddr2_odt : out std_logic;
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cntrl0_ddr2_dm : out std_logic_vector(1 downto 0);
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cntrl0_rst_dqs_div_in : in std_logic;
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cntrl0_rst_dqs_div_out : out std_logic;
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sys_clk_in : in std_logic;
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reset_in_n : in std_logic;
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cntrl0_burst_done : in std_logic;
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cntrl0_init_done : out std_logic;
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cntrl0_ar_done : out std_logic;
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cntrl0_user_data_valid : out std_logic;
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cntrl0_auto_ref_req : out std_logic;
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cntrl0_user_cmd_ack : out std_logic;
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cntrl0_user_command_register : in std_logic_vector(2 downto 0);
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cntrl0_clk_tb : out std_logic;
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cntrl0_clk90_tb : out std_logic;
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cntrl0_sys_rst_tb : out std_logic;
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cntrl0_sys_rst90_tb : out std_logic;
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cntrl0_sys_rst180_tb : out std_logic;
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cntrl0_user_output_data : out std_logic_vector(31 downto 0);
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cntrl0_user_input_data : in std_logic_vector(31 downto 0);
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cntrl0_user_data_mask : in std_logic_vector(3 downto 0);
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cntrl0_user_input_address : in std_logic_vector(24 downto 0);
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cntrl0_ddr2_dqs : inout std_logic_vector(1 downto 0);
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cntrl0_ddr2_dqs_n : inout std_logic_vector(1 downto 0);
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cntrl0_ddr2_ck : out std_logic_vector(0 downto 0);
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cntrl0_ddr2_ck_n : out std_logic_vector(0 downto 0)
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);
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end DDR2_Ram_Core;
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architecture arc_mem_interface_top of DDR2_Ram_Core is
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ATTRIBUTE X_CORE_INFO : STRING;
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ATTRIBUTE CORE_GENERATION_INFO : STRING;
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ATTRIBUTE X_CORE_INFO of arc_mem_interface_top : ARCHITECTURE IS "mig_v3_61_ddr2_sp3, Coregen 12.4";
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ATTRIBUTE CORE_GENERATION_INFO of arc_mem_interface_top : ARCHITECTURE IS "ddr2_sp3,mig_v3_61,{component_name=ddr2_sp3, data_width=16, memory_width=8, clk_width=1, bank_address=2, row_address=13, column_address=10, no_of_cs=1, cke_width=1, registered=0, data_mask=1, mask_enable=1, load_mode_register=0010100110010, ext_load_mode_register=0000000000000, language=VHDL, synthesis_tool=ISE, interface_type=DDR2_SDRAM, no_of_controllers=1}";
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component DDR2_Ram_Core_top_0
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port(
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ddr2_dq : inout std_logic_vector(15 downto 0);
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ddr2_a : out std_logic_vector(12 downto 0);
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ddr2_ba : out std_logic_vector(1 downto 0);
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ddr2_cke : out std_logic;
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ddr2_cs_n : out std_logic;
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ddr2_ras_n : out std_logic;
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ddr2_cas_n : out std_logic;
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ddr2_we_n : out std_logic;
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ddr2_odt : out std_logic;
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ddr2_dm : out std_logic_vector(1 downto 0);
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rst_dqs_div_in : in std_logic;
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rst_dqs_div_out : out std_logic;
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burst_done : in std_logic;
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init_done : out std_logic;
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ar_done : out std_logic;
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user_data_valid : out std_logic;
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auto_ref_req : out std_logic;
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user_cmd_ack : out std_logic;
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user_command_register : in std_logic_vector(2 downto 0);
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clk_tb : out std_logic;
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clk90_tb : out std_logic;
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sys_rst_tb : out std_logic;
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sys_rst90_tb : out std_logic;
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sys_rst180_tb : out std_logic;
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user_output_data : out std_logic_vector(31 downto 0);
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user_input_data : in std_logic_vector(31 downto 0);
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user_data_mask : in std_logic_vector(3 downto 0);
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user_input_address : in std_logic_vector(24 downto 0);
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ddr2_dqs : inout std_logic_vector(1 downto 0);
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ddr2_dqs_n : inout std_logic_vector(1 downto 0);
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ddr2_ck : out std_logic_vector(0 downto 0);
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ddr2_ck_n : out std_logic_vector(0 downto 0);
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clk_int : in std_logic;
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clk90_int : in std_logic;
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wait_200us : in std_logic;
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sys_rst : in std_logic;
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sys_rst90 : in std_logic;
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sys_rst180 : in std_logic;
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delay_sel_val : in std_logic_vector(4 downto 0);
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--Debug ports
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dbg_delay_sel : out std_logic_vector(4 downto 0);
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dbg_rst_calib : out std_logic;
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vio_out_dqs : in std_logic_vector(4 downto 0);
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vio_out_dqs_en : in std_logic;
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vio_out_rst_dqs_div : in std_logic_vector(4 downto 0);
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vio_out_rst_dqs_div_en : in std_logic
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);
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end component;
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component DDR2_Ram_Core_infrastructure_top
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port (
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sys_clkb : in std_logic;
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sys_clk : in std_logic;
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sys_clk_in : in std_logic;
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reset_in_n : in std_logic;
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wait_200us : out std_logic;
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delay_sel_val1_val : out std_logic_vector(4 downto 0);
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sys_rst_val : out std_logic;
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sys_rst90_val : out std_logic;
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clk_int_val : out std_logic;
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clk90_int_val : out std_logic;
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sys_rst180_val : out std_logic;
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dbg_phase_cnt : out std_logic_vector(4 downto 0);
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dbg_cnt : out std_logic_vector(5 downto 0);
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dbg_trans_onedtct : out std_logic;
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dbg_trans_twodtct : out std_logic;
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dbg_enb_trans_two_dtct : out std_logic
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);
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end component;
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signal sys_rst : std_logic;
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signal wait_200us : std_logic;
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signal sys_rst90 : std_logic;
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signal sys_rst180 : std_logic;
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signal clk_0 : std_logic;
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signal clk90_0 : std_logic;
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signal delay_sel : std_logic_vector(4 downto 0);
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-- debug signals
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signal dbg_phase_cnt : std_logic_vector(4 downto 0);
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signal dbg_cnt : std_logic_vector(5 downto 0);
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signal dbg_trans_onedtct : std_logic;
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signal dbg_trans_twodtct : std_logic;
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signal dbg_enb_trans_two_dtct : std_logic;
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signal dbg_delay_sel : std_logic_vector(4 downto 0);
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signal dbg_rst_calib : std_logic;
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-- chipscope signals
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signal dbg_data : std_logic_vector(19 downto 0);
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signal dbg_trig : std_logic_vector(3 downto 0);
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signal control0 : std_logic_vector(35 downto 0);
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signal control1 : std_logic_vector(35 downto 0);
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signal vio_out_dqs : std_logic_vector(4 downto 0);
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signal vio_out_dqs_en : std_logic;
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signal vio_out_rst_dqs_div : std_logic_vector(4 downto 0);
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signal vio_out_rst_dqs_div_en : std_logic;
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signal vio_out : std_logic_vector(11 downto 0);
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signal sys_clkb : std_logic;
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signal sys_clk : std_logic;
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begin
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sys_clkb <= '0';
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sys_clk <= '0';
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top_00 : DDR2_Ram_Core_top_0
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port map (
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ddr2_dq => cntrl0_ddr2_dq,
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ddr2_a => cntrl0_ddr2_a,
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ddr2_ba => cntrl0_ddr2_ba,
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ddr2_cke => cntrl0_ddr2_cke,
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ddr2_cs_n => cntrl0_ddr2_cs_n,
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ddr2_ras_n => cntrl0_ddr2_ras_n,
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ddr2_cas_n => cntrl0_ddr2_cas_n,
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ddr2_we_n => cntrl0_ddr2_we_n,
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ddr2_odt => cntrl0_ddr2_odt,
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ddr2_dm => cntrl0_ddr2_dm,
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rst_dqs_div_in => cntrl0_rst_dqs_div_in,
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rst_dqs_div_out => cntrl0_rst_dqs_div_out,
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burst_done => cntrl0_burst_done,
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init_done => cntrl0_init_done,
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ar_done => cntrl0_ar_done,
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user_data_valid => cntrl0_user_data_valid,
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auto_ref_req => cntrl0_auto_ref_req,
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user_cmd_ack => cntrl0_user_cmd_ack,
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user_command_register => cntrl0_user_command_register,
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clk_tb => cntrl0_clk_tb,
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clk90_tb => cntrl0_clk90_tb,
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sys_rst_tb => cntrl0_sys_rst_tb,
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sys_rst90_tb => cntrl0_sys_rst90_tb,
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sys_rst180_tb => cntrl0_sys_rst180_tb,
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user_output_data => cntrl0_user_output_data,
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user_input_data => cntrl0_user_input_data,
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user_data_mask => cntrl0_user_data_mask,
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user_input_address => cntrl0_user_input_address,
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ddr2_dqs => cntrl0_ddr2_dqs,
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ddr2_dqs_n => cntrl0_ddr2_dqs_n,
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ddr2_ck => cntrl0_ddr2_ck,
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ddr2_ck_n => cntrl0_ddr2_ck_n,
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wait_200us => wait_200us,
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delay_sel_val => delay_sel,
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clk_int => clk_0,
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clk90_int => clk90_0,
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sys_rst => sys_rst,
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sys_rst90 => sys_rst90,
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sys_rst180 => sys_rst180,
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--Debug signals
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dbg_delay_sel => dbg_delay_sel,
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dbg_rst_calib => dbg_rst_calib,
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vio_out_dqs => vio_out_dqs,
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vio_out_dqs_en => vio_out_dqs_en,
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vio_out_rst_dqs_div => vio_out_rst_dqs_div,
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vio_out_rst_dqs_div_en => vio_out_rst_dqs_div_en
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);
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infrastructure_top0 : DDR2_Ram_Core_infrastructure_top
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port map (
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wait_200us => wait_200us,
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delay_sel_val1_val => delay_sel,
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clk_int_val => clk_0,
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clk90_int_val => clk90_0,
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sys_rst_val => sys_rst,
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sys_rst90_val => sys_rst90,
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sys_rst180_val => sys_rst180,
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dbg_phase_cnt => dbg_phase_cnt,
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dbg_cnt => dbg_cnt,
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dbg_trans_onedtct => dbg_trans_onedtct,
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dbg_trans_twodtct => dbg_trans_twodtct,
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dbg_enb_trans_two_dtct => dbg_enb_trans_two_dtct,
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sys_clkb => sys_clkb,
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sys_clk => sys_clk,
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sys_clk_in => sys_clk_in,
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reset_in_n => reset_in_n
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);
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end arc_mem_interface_top;
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