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Subversion Repositories ddr2_sdram

[/] [ddr2_sdram/] [trunk/] [ipcore_dir/] [DDR2_Ram_Core/] [user_design/] [rtl/] [DDR2_Ram_Core_tap_dly.vhd] - Blame information for rev 2

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--*****************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--*****************************************************************************
--   ____  ____
--  /   /\/   /
-- /___/  \  /   Vendor             : Xilinx
-- \   \   \/    Version            : 3.6.1
--  \   \        Application        : MIG
--  /   /        Filename           : DDR2_Ram_Core_tap_dly.vhd
-- /___/   /\    Date Last Modified : $Date: 2010/11/26 18:25:42 $
-- \   \  /  \   Date Created       : Mon May 2 2005
--  \___\/\___\
-- Device      : Spartan-3/3A/3A-DSP
-- Design Name : DDR2 SDRAM
-- Purpose     :This module generates a 32 bit tap delay register used by the
--              cal_ctl module to find out the phase transitions.
--*****************************************************************************
 
library ieee;
library UNISIM;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use UNISIM.VCOMPONENTS.all;
 
 
entity DDR2_Ram_Core_tap_dly is
  port (
    clk   : in  std_logic;
    reset : in  std_logic;
    tapin : in  std_logic;
    flop2 : out std_logic_vector(31 downto 0)
    );
end DDR2_Ram_Core_tap_dly;
 
architecture arc_tap_dly of DDR2_Ram_Core_tap_dly is
 
  signal tap        : std_logic_vector(31 downto 0);
  signal flop1      : std_logic_vector(31 downto 0);
  signal high       : std_logic;
  signal low        : std_logic;
  signal flop2_xnor : std_logic_vector(30 downto 0);
  signal reset_r    : std_logic;
 
  attribute syn_preserve : boolean;
 
  attribute syn_preserve of tap   : signal is true;
  attribute syn_preserve of flop1 : signal is true;
 
 
begin
 
  process(clk)
  begin
    if(clk'event and clk='1') then
      reset_r <= reset;
    end if;
  end process;
 
  high <= '1';
  low  <= '0';
 
  l0 : LUT4 generic map (INIT => x"e2e2")
    port map (
      I0 => high,
      I1 => tapin,
      I2 => low,
      I3 => high,
      O  => tap(0)
      );
 
  l1 : LUT4 generic map (INIT => x"e2e2")
    port map (
      I0 => high,
      I1 => tap(0),
      I2 => low,
      I3 => high,
      O  => tap(1)
      );
  l2 : LUT4 generic map (INIT => x"e2e2")
    port map (
      I0 => high,
      I1 => tap(1),
      I2 => low,
      I3 => high,
      O  => tap(2)
      );
  l3 : LUT4 generic map (INIT => x"e2e2")
    port map (
      I0 => high,
      I1 => tap(2),
      I2 => low,
      I3 => high,
      O  => tap(3)
      );
  l4 : LUT4 generic map (INIT => x"e2e2")
    port map (
      I0 => high,
      I1 => tap(3),
      I2 => low,
      I3 => high,
      O  => tap(4)
      );
  l5 : LUT4 generic map (INIT => x"e2e2")
    port map (
      I0 => high,
      I1 => tap(4),
      I2 => low,
      I3 => high,
      O  => tap(5)
      );
  l6 : LUT4 generic map (INIT => x"e2e2")
    port map (
      I0 => high,
      I1 => tap(5),
      I2 => low,
      I3 => high,
      O  => tap(6)
      );
  l7 : LUT4 generic map (INIT => x"e2e2")
    port map (
      I0 => high,
      I1 => tap(6),
      I2 => low,
      I3 => high,
      O  => tap(7)
      );
  l8 : LUT4 generic map (INIT => x"e2e2")
    port map (
      I0 => high,
      I1 => tap(7),
      I2 => low,
      I3 => high,
      O  => tap(8)
      );
  l9 : LUT4 generic map (INIT => x"e2e2")
    port map (
      I0 => high,
      I1 => tap(8),
      I2 => low,
      I3 => high,
      O  => tap(9)
      );
  l10 : LUT4 generic map (INIT => x"e2e2")
    port map (
      I0 => high,
      I1 => tap(9),
      I2 => low,
      I3 => high,
      O  => tap(10)
      );
  l11 : LUT4 generic map (INIT => x"e2e2")
    port map (
      I0 => high,
      I1 => tap(10),
      I2 => low,
      I3 => high,
      O  => tap(11)
      );
  l12 : LUT4 generic map (INIT => x"e2e2")
    port map (
      I0 => high,
      I1 => tap(11),
      I2 => low,
      I3 => high,
      O  => tap(12)
      );
  l13 : LUT4 generic map (INIT => x"e2e2")
    port map (
      I0 => high,
      I1 => tap(12),
      I2 => low,
      I3 => high,
      O  => tap(13)
      );
  l14 : LUT4 generic map (INIT => x"e2e2")
    port map (
      I0 => high,
      I1 => tap(13),
      I2 => low,
      I3 => high,
      O  => tap(14)
      );
  l15 : LUT4 generic map (INIT => x"e2e2")
    port map (
      I0 => high,
      I1 => tap(14),
      I2 => low,
      I3 => high,
      O  => tap(15)
      );
  l16 : LUT4 generic map (INIT => x"e2e2")
    port map (
      I0 => high,
      I1 => tap(15),
      I2 => low,
      I3 => high,
      O  => tap(16)
      );
  l17 : LUT4 generic map (INIT => x"e2e2")
    port map (
      I0 => high,
      I1 => tap(16),
      I2 => low,
      I3 => high,
      O  => tap(17)
      );
  l18 : LUT4 generic map (INIT => x"e2e2")
    port map (
      I0 => high,
      I1 => tap(17),
      I2 => low,
      I3 => high,
      O  => tap(18)
      );
  l19 : LUT4 generic map (INIT => x"e2e2")
    port map (
      I0 => high,
      I1 => tap(18),
      I2 => low,
      I3 => high,
      O  => tap(19)
      );
  l20 : LUT4 generic map (INIT => x"e2e2")
    port map (
      I0 => high,
      I1 => tap(19),
      I2 => low,
      I3 => high,
      O  => tap(20)
      );
  l21 : LUT4 generic map (INIT => x"e2e2")
    port map (
      I0 => high,
      I1 => tap(20),
      I2 => low,
      I3 => high,
      O  => tap(21)
      );
  l22 : LUT4 generic map (INIT => x"e2e2")
    port map (
      I0 => high,
      I1 => tap(21),
      I2 => low,
      I3 => high,
      O  => tap(22)
      );
  l23 : LUT4 generic map (INIT => x"e2e2")
    port map (
      I0 => high,
      I1 => tap(22),
      I2 => low,
      I3 => high,
      O  => tap(23)
      );
  l24 : LUT4 generic map (INIT => x"e2e2")
    port map (
      I0 => high,
      I1 => tap(23),
      I2 => low,
      I3 => high,
      O  => tap(24)
      );
  l25 : LUT4 generic map (INIT => x"e2e2")
    port map (
      I0 => high,
      I1 => tap(24),
      I2 => low,
      I3 => high,
      O  => tap(25)
      );
  l26 : LUT4 generic map (INIT => x"e2e2")
    port map (
      I0 => high,
      I1 => tap(25),
      I2 => low,
      I3 => high,
      O  => tap(26)
      );
  l27 : LUT4 generic map (INIT => x"e2e2")
    port map (
      I0 => high,
      I1 => tap(26),
      I2 => low,
      I3 => high,
      O  => tap(27)
      );
  l28 : LUT4 generic map (INIT => x"e2e2")
    port map (
      I0 => high,
      I1 => tap(27),
      I2 => low,
      I3 => high,
      O  => tap(28)
      );
  l29 : LUT4 generic map (INIT => x"e2e2")
    port map (
      I0 => high,
      I1 => tap(28),
      I2 => low,
      I3 => high,
      O  => tap(29)
      );
  l30 : LUT4 generic map (INIT => x"e2e2")
    port map (
      I0 => high,
      I1 => tap(29),
      I2 => low,
      I3 => high,
      O  => tap(30)
      );
  l31 : LUT4 generic map (INIT => x"e2e2")
    port map (
      I0 => high,
      I1 => tap(30),
      I2 => low,
      I3 => high,
      O  => tap(31)
      );
 
  gen_tap1 : for tap1_i in 0 to 31 generate
    r : FDR port map (
      Q => flop1(tap1_i),
      C => clk,
      D => tap(tap1_i),
      R => reset_r
      );
  end generate;
 
  gen_asgn : for asgn_i in 0 to 30 generate
    flop2_xnor(asgn_i)  <= flop1(asgn_i) xnor flop1(asgn_i+1);
  end generate;
 
  gen_tap2 : for tap2_i in 0 to 30 generate
    u : FDR port map (
      Q => flop2(tap2_i),
      C => clk,
      D => flop2_xnor(tap2_i),
      R => reset_r
      );
  end generate;
 
  u31 : FDR
    port map (
      Q => flop2(31),
      C => clk,
      D => flop1(31),
      R => reset_r
      );
 
end arc_tap_dly;

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Subversion Repositories ddr2_sdram

[/] [ddr2_sdram/] [trunk/] [ipcore_dir/] [DDR2_Ram_Core/] [user_design/] [rtl/] [DDR2_Ram_Core_tap_dly.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	john_fpga	`--*****************************************************************************`
2			`-- DISCLAIMER OF LIABILITY`
3			`--`
4			`-- This file contains proprietary and confidential information of`
5			`-- Xilinx, Inc. ("Xilinx"), that is distributed under a license`
6			`-- from Xilinx, and may be used, copied and/or disclosed only`
7			`-- pursuant to the terms of a valid license agreement with Xilinx.`
8			`--`
9			`-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION`
10			`-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER`
11			`-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT`
12			`-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,`
13			`-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx`
14			`-- does not warrant that functions included in the Materials will`
15			`-- meet the requirements of Licensee, or that the operation of the`
16			`-- Materials will be uninterrupted or error-free, or that defects`
17			`-- in the Materials will be corrected. Furthermore, Xilinx does`
18			`-- not warrant or make any representations regarding use, or the`
19			`-- results of the use, of the Materials in terms of correctness,`
20			`-- accuracy, reliability or otherwise.`
21			`--`
22			`-- Xilinx products are not designed or intended to be fail-safe,`
23			`-- or for use in any application requiring fail-safe performance,`
24			`-- such as life-support or safety devices or systems, Class III`
25			`-- medical devices, nuclear facilities, applications related to`
26			`-- the deployment of airbags, or any other applications that could`
27			`-- lead to death, personal injury or severe property or`
28			`-- environmental damage (individually and collectively, "critical`
29			`-- applications"). Customer assumes the sole risk and liability`
30			`-- of any use of Xilinx products in critical applications,`
31			`-- subject only to applicable laws and regulations governing`
32			`-- limitations on product liability.`
33			`--`
34			`-- Copyright 2005, 2006, 2007 Xilinx, Inc.`
35			`-- All rights reserved.`
36			`--`
37			`-- This disclaimer and copyright notice must be retained as part`
38			`-- of this file at all times.`
39			`--*****************************************************************************`
40			`-- ____ ____`
41			`-- / /\/ /`
42			`-- /___/ \ / Vendor : Xilinx`
43			`-- \ \ \/ Version : 3.6.1`
44			`-- \ \ Application : MIG`
45			`-- / / Filename : DDR2_Ram_Core_tap_dly.vhd`
46			`-- /___/ /\ Date Last Modified : $Date: 2010/11/26 18:25:42 $`
47			`-- \ \ / \ Date Created : Mon May 2 2005`
48			`-- \___\/\___\`
49			`-- Device : Spartan-3/3A/3A-DSP`
50			`-- Design Name : DDR2 SDRAM`
51			`-- Purpose :This module generates a 32 bit tap delay register used by the`
52			`-- cal_ctl module to find out the phase transitions.`
53			`--*****************************************************************************`
54
55			`library ieee;`
56			`library UNISIM;`
57			`use ieee.std_logic_1164.all;`
58			`use ieee.std_logic_unsigned.all;`
59			`use UNISIM.VCOMPONENTS.all;`
60
61
62			`entity DDR2_Ram_Core_tap_dly is`
63			`port (`
64			`clk : in std_logic;`
65			`reset : in std_logic;`
66			`tapin : in std_logic;`
67			`flop2 : out std_logic_vector(31 downto 0)`
68			`);`
69			`end DDR2_Ram_Core_tap_dly;`
70
71			`architecture arc_tap_dly of DDR2_Ram_Core_tap_dly is`
72
73			`signal tap : std_logic_vector(31 downto 0);`
74			`signal flop1 : std_logic_vector(31 downto 0);`
75			`signal high : std_logic;`
76			`signal low : std_logic;`
77			`signal flop2_xnor : std_logic_vector(30 downto 0);`
78			`signal reset_r : std_logic;`
79
80			`attribute syn_preserve : boolean;`
81
82			`attribute syn_preserve of tap : signal is true;`
83			`attribute syn_preserve of flop1 : signal is true;`
84
85
86			`begin`
87
88			`process(clk)`
89			`begin`
90			`if(clk'event and clk='1') then`
91			`reset_r <= reset;`
92			`end if;`
93			`end process;`
94
95			`high <= '1';`
96			`low <= '0';`
97
98			`l0 : LUT4 generic map (INIT => x"e2e2")`
99			`port map (`
100			`I0 => high,`
101			`I1 => tapin,`
102			`I2 => low,`
103			`I3 => high,`
104			`O => tap(0)`
105			`);`
106
107			`l1 : LUT4 generic map (INIT => x"e2e2")`
108			`port map (`
109			`I0 => high,`
110			`I1 => tap(0),`
111			`I2 => low,`
112			`I3 => high,`
113			`O => tap(1)`
114			`);`
115			`l2 : LUT4 generic map (INIT => x"e2e2")`
116			`port map (`
117			`I0 => high,`
118			`I1 => tap(1),`
119			`I2 => low,`
120			`I3 => high,`
121			`O => tap(2)`
122			`);`
123			`l3 : LUT4 generic map (INIT => x"e2e2")`
124			`port map (`
125			`I0 => high,`
126			`I1 => tap(2),`
127			`I2 => low,`
128			`I3 => high,`
129			`O => tap(3)`
130			`);`
131			`l4 : LUT4 generic map (INIT => x"e2e2")`
132			`port map (`
133			`I0 => high,`
134			`I1 => tap(3),`
135			`I2 => low,`
136			`I3 => high,`
137			`O => tap(4)`
138			`);`
139			`l5 : LUT4 generic map (INIT => x"e2e2")`
140			`port map (`
141			`I0 => high,`
142			`I1 => tap(4),`
143			`I2 => low,`
144			`I3 => high,`
145			`O => tap(5)`
146			`);`
147			`l6 : LUT4 generic map (INIT => x"e2e2")`
148			`port map (`
149			`I0 => high,`
150			`I1 => tap(5),`
151			`I2 => low,`
152			`I3 => high,`
153			`O => tap(6)`
154			`);`
155			`l7 : LUT4 generic map (INIT => x"e2e2")`
156			`port map (`
157			`I0 => high,`
158			`I1 => tap(6),`
159			`I2 => low,`
160			`I3 => high,`
161			`O => tap(7)`
162			`);`
163			`l8 : LUT4 generic map (INIT => x"e2e2")`
164			`port map (`
165			`I0 => high,`
166			`I1 => tap(7),`
167			`I2 => low,`
168			`I3 => high,`
169			`O => tap(8)`
170			`);`
171			`l9 : LUT4 generic map (INIT => x"e2e2")`
172			`port map (`
173			`I0 => high,`
174			`I1 => tap(8),`
175			`I2 => low,`
176			`I3 => high,`
177			`O => tap(9)`
178			`);`
179			`l10 : LUT4 generic map (INIT => x"e2e2")`
180			`port map (`
181			`I0 => high,`
182			`I1 => tap(9),`
183			`I2 => low,`
184			`I3 => high,`
185			`O => tap(10)`
186			`);`
187			`l11 : LUT4 generic map (INIT => x"e2e2")`
188			`port map (`
189			`I0 => high,`
190			`I1 => tap(10),`
191			`I2 => low,`
192			`I3 => high,`
193			`O => tap(11)`
194			`);`
195			`l12 : LUT4 generic map (INIT => x"e2e2")`
196			`port map (`
197			`I0 => high,`
198			`I1 => tap(11),`
199			`I2 => low,`
200			`I3 => high,`
201			`O => tap(12)`
202			`);`
203			`l13 : LUT4 generic map (INIT => x"e2e2")`
204			`port map (`
205			`I0 => high,`
206			`I1 => tap(12),`
207			`I2 => low,`
208			`I3 => high,`
209			`O => tap(13)`
210			`);`
211			`l14 : LUT4 generic map (INIT => x"e2e2")`
212			`port map (`
213			`I0 => high,`
214			`I1 => tap(13),`
215			`I2 => low,`
216			`I3 => high,`
217			`O => tap(14)`
218			`);`
219			`l15 : LUT4 generic map (INIT => x"e2e2")`
220			`port map (`
221			`I0 => high,`
222			`I1 => tap(14),`
223			`I2 => low,`
224			`I3 => high,`
225			`O => tap(15)`
226			`);`
227			`l16 : LUT4 generic map (INIT => x"e2e2")`
228			`port map (`
229			`I0 => high,`
230			`I1 => tap(15),`
231			`I2 => low,`
232			`I3 => high,`
233			`O => tap(16)`
234			`);`
235			`l17 : LUT4 generic map (INIT => x"e2e2")`
236			`port map (`
237			`I0 => high,`
238			`I1 => tap(16),`
239			`I2 => low,`
240			`I3 => high,`
241			`O => tap(17)`
242			`);`
243			`l18 : LUT4 generic map (INIT => x"e2e2")`
244			`port map (`
245			`I0 => high,`
246			`I1 => tap(17),`
247			`I2 => low,`
248			`I3 => high,`
249			`O => tap(18)`
250			`);`
251			`l19 : LUT4 generic map (INIT => x"e2e2")`
252			`port map (`
253			`I0 => high,`
254			`I1 => tap(18),`
255			`I2 => low,`
256			`I3 => high,`
257			`O => tap(19)`
258			`);`
259			`l20 : LUT4 generic map (INIT => x"e2e2")`
260			`port map (`
261			`I0 => high,`
262			`I1 => tap(19),`
263			`I2 => low,`
264			`I3 => high,`
265			`O => tap(20)`
266			`);`
267			`l21 : LUT4 generic map (INIT => x"e2e2")`
268			`port map (`
269			`I0 => high,`
270			`I1 => tap(20),`
271			`I2 => low,`
272			`I3 => high,`
273			`O => tap(21)`
274			`);`
275			`l22 : LUT4 generic map (INIT => x"e2e2")`
276			`port map (`
277			`I0 => high,`
278			`I1 => tap(21),`
279			`I2 => low,`
280			`I3 => high,`
281			`O => tap(22)`
282			`);`
283			`l23 : LUT4 generic map (INIT => x"e2e2")`
284			`port map (`
285			`I0 => high,`
286			`I1 => tap(22),`
287			`I2 => low,`
288			`I3 => high,`
289			`O => tap(23)`
290			`);`
291			`l24 : LUT4 generic map (INIT => x"e2e2")`
292			`port map (`
293			`I0 => high,`
294			`I1 => tap(23),`
295			`I2 => low,`
296			`I3 => high,`
297			`O => tap(24)`
298			`);`
299			`l25 : LUT4 generic map (INIT => x"e2e2")`
300			`port map (`
301			`I0 => high,`
302			`I1 => tap(24),`
303			`I2 => low,`
304			`I3 => high,`
305			`O => tap(25)`
306			`);`
307			`l26 : LUT4 generic map (INIT => x"e2e2")`
308			`port map (`
309			`I0 => high,`
310			`I1 => tap(25),`
311			`I2 => low,`
312			`I3 => high,`
313			`O => tap(26)`
314			`);`
315			`l27 : LUT4 generic map (INIT => x"e2e2")`
316			`port map (`
317			`I0 => high,`
318			`I1 => tap(26),`
319			`I2 => low,`
320			`I3 => high,`
321			`O => tap(27)`
322			`);`
323			`l28 : LUT4 generic map (INIT => x"e2e2")`
324			`port map (`
325			`I0 => high,`
326			`I1 => tap(27),`
327			`I2 => low,`
328			`I3 => high,`
329			`O => tap(28)`
330			`);`
331			`l29 : LUT4 generic map (INIT => x"e2e2")`
332			`port map (`
333			`I0 => high,`
334			`I1 => tap(28),`
335			`I2 => low,`
336			`I3 => high,`
337			`O => tap(29)`
338			`);`
339			`l30 : LUT4 generic map (INIT => x"e2e2")`
340			`port map (`
341			`I0 => high,`
342			`I1 => tap(29),`
343			`I2 => low,`
344			`I3 => high,`
345			`O => tap(30)`
346			`);`
347			`l31 : LUT4 generic map (INIT => x"e2e2")`
348			`port map (`
349			`I0 => high,`
350			`I1 => tap(30),`
351			`I2 => low,`
352			`I3 => high,`
353			`O => tap(31)`
354			`);`
355
356			`gen_tap1 : for tap1_i in 0 to 31 generate`
357			`r : FDR port map (`
358			`Q => flop1(tap1_i),`
359			`C => clk,`
360			`D => tap(tap1_i),`
361			`R => reset_r`
362			`);`
363			`end generate;`
364
365			`gen_asgn : for asgn_i in 0 to 30 generate`
366			`flop2_xnor(asgn_i) <= flop1(asgn_i) xnor flop1(asgn_i+1);`
367			`end generate;`
368
369			`gen_tap2 : for tap2_i in 0 to 30 generate`
370			`u : FDR port map (`
371			`Q => flop2(tap2_i),`
372			`C => clk,`
373			`D => flop2_xnor(tap2_i),`
374			`R => reset_r`
375			`);`
376			`end generate;`
377
378			`u31 : FDR`
379			`port map (`
380			`Q => flop2(31),`
381			`C => clk,`
382			`D => flop1(31),`
383			`R => reset_r`
384			`);`
385
386			`end arc_tap_dly;`