URL https://opencores.org/ocsvn/ddr2_sdram/ddr2_sdram/trunk

Subversion Repositories ddr2_sdram

[/] [ddr2_sdram/] [trunk/] [iseconfig/] [Prj_12_DDR2.projectmgr] - Blame information for rev 2

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         2
         /Top_Modul_VHDL - Verhalten F:|Data_Temp_Ordner|Xilinx|Projekte|Test_Prj_VHDL|Prj_12_DDR2|Prj_12_DDR2|Top_Modul_VHDL.vhd/INST_DDR2_RAM_CORE - DDR2_Ram_Core - arc_mem_interface_top
         /Top_Modul_VHDL - Verhalten F:|Data_Temp_Ordner|Xilinx|Projekte|Test_Prj_VHDL|Prj_12_DDR2|Prj_12_DDR2|Top_Modul_VHDL.vhd/INST_DDR2_RAM_CORE - DDR2_Ram_Core - arc_mem_interface_top/infrastructure_top0 - DDR2_Ram_Core_infrastructure_top - arc
         /Top_Modul_VHDL - Verhalten F:|Data_Temp_Ordner|Xilinx|Projekte|Test_Prj_VHDL|Prj_12_DDR2|Prj_12_DDR2|Top_Modul_VHDL.vhd/INST_DDR2_RAM_CORE - DDR2_Ram_Core - arc_mem_interface_top/top_00 - DDR2_Ram_Core_top_0 - arc
      
      
         Prj_12_DDR2
      
      0
      0
      000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000238000000020000000000000000000000000200000064ffffffff000000810000000300000002000002380000000100000003000000000000000100000003
      true
      Prj_12_DDR2
   
   
      
         1
         Design Utilities
      
      
         
      
      0
      0
      000000ff000000000000000100000001000000000000000000000000000000000000000000000001bd000000010000000100000000000000000000000064ffffffff000000810000000000000001000001bd0000000100000000
      false
      
   
   
      
         1
      
      
      0
      0
      000000ff00000000000000010000000000000000010000000000000000000000000000000000000392000000040101000100000000000000000000000064ffffffff000000810000000000000004000000e60000000100000000000000240000000100000000000000660000000100000000000002220000000100000000
      false
      Buttons_VHDL.vhd
   
   
      
         1
         work
      
      
      0
      0
      000000ff00000000000000010000000000000000010000000000000000000000000000000000000109000000010001000100000000000000000000000064ffffffff000000810000000000000001000001090000000100000000
      false
      work
   
   
      
         1
         Design Utilities
         Implement Design
         Synthesize - XST
         User Constraints
      
      
         
      
      0
      0
      000000ff000000000000000100000001000000000000000000000000000000000000000000000001bd000000010000000100000000000000000000000064ffffffff000000810000000000000001000001bd0000000100000000
      false
      
   
   000000ff00000000000000020000015d0000011c01000000050100000002
   Implementation
   
      
         1
      
      
         Edit Constraints (Text)
      
      0
      0
      000000ff000000000000000100000001000000000000000000000000000000000000000000000001bd000000010000000100000000000000000000000064ffffffff000000810000000000000001000001bd0000000100000000
      false
      Edit Constraints (Text)
   


Line No.	Rev	Author	Line
1	2	john_fpga
2
3
4
5
6
7
8
9			`2`
10			`/Top_Modul_VHDL - Verhalten F:\|Data_Temp_Ordner\|Xilinx\|Projekte\|Test_Prj_VHDL\|Prj_12_DDR2\|Prj_12_DDR2\|Top_Modul_VHDL.vhd/INST_DDR2_RAM_CORE - DDR2_Ram_Core - arc_mem_interface_top`
11			`/Top_Modul_VHDL - Verhalten F:\|Data_Temp_Ordner\|Xilinx\|Projekte\|Test_Prj_VHDL\|Prj_12_DDR2\|Prj_12_DDR2\|Top_Modul_VHDL.vhd/INST_DDR2_RAM_CORE - DDR2_Ram_Core - arc_mem_interface_top/infrastructure_top0 - DDR2_Ram_Core_infrastructure_top - arc`
12			`/Top_Modul_VHDL - Verhalten F:\|Data_Temp_Ordner\|Xilinx\|Projekte\|Test_Prj_VHDL\|Prj_12_DDR2\|Prj_12_DDR2\|Top_Modul_VHDL.vhd/INST_DDR2_RAM_CORE - DDR2_Ram_Core - arc_mem_interface_top/top_00 - DDR2_Ram_Core_top_0 - arc`
13
14
15			`Prj_12_DDR2`
16
17			`0`
18			`0`
19			`000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000238000000020000000000000000000000000200000064ffffffff000000810000000300000002000002380000000100000003000000000000000100000003`
20			`true`
21			`Prj_12_DDR2`
22
23
24
25			`1`
26			`Design Utilities`
27
28
29
30
31			`0`
32			`0`
33			`000000ff000000000000000100000001000000000000000000000000000000000000000000000001bd000000010000000100000000000000000000000064ffffffff000000810000000000000001000001bd0000000100000000`
34			`false`
35
36
37
38
39			`1`
40
41
42			`0`
43			`0`
44			`000000ff00000000000000010000000000000000010000000000000000000000000000000000000392000000040101000100000000000000000000000064ffffffff000000810000000000000004000000e60000000100000000000000240000000100000000000000660000000100000000000002220000000100000000`
45			`false`
46			`Buttons_VHDL.vhd`
47
48
49
50			`1`
51			`work`
52
53
54			`0`
55			`0`
56			`000000ff00000000000000010000000000000000010000000000000000000000000000000000000109000000010001000100000000000000000000000064ffffffff000000810000000000000001000001090000000100000000`
57			`false`
58			`work`
59
60
61
62			`1`
63			`Design Utilities`
64			`Implement Design`
65			`Synthesize - XST`
66			`User Constraints`
67
68
69
70
71			`0`
72			`0`
73			`000000ff000000000000000100000001000000000000000000000000000000000000000000000001bd000000010000000100000000000000000000000064ffffffff000000810000000000000001000001bd0000000100000000`
74			`false`
75
76
77			`000000ff00000000000000020000015d0000011c01000000050100000002`
78			`Implementation`
79
80
81			`1`
82
83
84			`Edit Constraints (Text)`
85
86			`0`
87			`0`
88			`000000ff000000000000000100000001000000000000000000000000000000000000000000000001bd000000010000000100000000000000000000000064ffffffff000000810000000000000001000001bd0000000100000000`
89			`false`
90			`Edit Constraints (Text)`
91
92

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Subversion Repositories ddr2_sdram

[/] [ddr2_sdram/] [trunk/] [iseconfig/] [Prj_12_DDR2.projectmgr] - Blame information for rev 2