1 |
3 |
plutonium |
-- DDS Frequency Synthesizer
|
2 |
|
|
--
|
3 |
|
|
-- Output frequency is f=ftw_i/2^ftw_width*fclk
|
4 |
|
|
-- Output initial phase is phi=phase_i/2^phase_width*2*pi
|
5 |
|
|
--
|
6 |
|
|
-- Copyright (C) 2009 Martin Kumm
|
7 |
|
|
--
|
8 |
|
|
-- This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
|
9 |
|
|
-- as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version.
|
10 |
|
|
--
|
11 |
|
|
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
|
12 |
|
|
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
|
13 |
|
|
--
|
14 |
|
|
-- You should have received a copy of the GNU General Public License along with this program;
|
15 |
|
|
-- if not, see <http://www.gnu.org/licenses/>.
|
16 |
|
|
|
17 |
|
|
-- Package Definition
|
18 |
|
|
|
19 |
|
|
library ieee;
|
20 |
|
|
use ieee.std_logic_1164.all;
|
21 |
|
|
use IEEE.STD_LOGIC_arith.all;
|
22 |
|
|
use IEEE.STD_LOGIC_unsigned.all;
|
23 |
|
|
use work.sine_lut_pkg.all;
|
24 |
|
|
|
25 |
|
|
package dds_synthesizer_pkg is
|
26 |
|
|
component dds_synthesizer
|
27 |
|
|
generic(
|
28 |
|
|
ftw_width : integer
|
29 |
|
|
);
|
30 |
|
|
port(
|
31 |
|
|
clk_i : in std_logic;
|
32 |
|
|
rst_i : in std_logic;
|
33 |
|
|
ftw_i : in std_logic_vector(ftw_width-1 downto 0);
|
34 |
|
|
phase_i : in std_logic_vector(PHASE_WIDTH-1 downto 0);
|
35 |
|
|
phase_o : out std_logic_vector(PHASE_WIDTH-1 downto 0);
|
36 |
|
|
ampl_o : out std_logic_vector(AMPL_WIDTH-1 downto 0)
|
37 |
|
|
);
|
38 |
|
|
end component;
|
39 |
|
|
end dds_synthesizer_pkg;
|
40 |
|
|
|
41 |
|
|
package body dds_synthesizer_pkg is
|
42 |
|
|
end dds_synthesizer_pkg;
|
43 |
|
|
|
44 |
|
|
-- Entity Definition
|
45 |
|
|
|
46 |
|
|
library ieee;
|
47 |
|
|
use ieee.std_logic_1164.all;
|
48 |
|
|
use IEEE.STD_LOGIC_arith.all;
|
49 |
|
|
use IEEE.STD_LOGIC_unsigned.all;
|
50 |
|
|
use work.sine_lut_pkg.all;
|
51 |
|
|
|
52 |
|
|
entity dds_synthesizer is
|
53 |
|
|
generic(
|
54 |
|
|
ftw_width : integer := 32
|
55 |
|
|
);
|
56 |
|
|
port(
|
57 |
|
|
clk_i : in std_logic;
|
58 |
|
|
rst_i : in std_logic;
|
59 |
|
|
ftw_i : in std_logic_vector(ftw_width-1 downto 0);
|
60 |
|
|
phase_i : in std_logic_vector(PHASE_WIDTH-1 downto 0);
|
61 |
|
|
phase_o : out std_logic_vector(PHASE_WIDTH-1 downto 0);
|
62 |
|
|
ampl_o : out std_logic_vector(AMPL_WIDTH-1 downto 0)
|
63 |
|
|
);
|
64 |
|
|
end dds_synthesizer;
|
65 |
|
|
|
66 |
|
|
architecture dds_synthesizer_arch of dds_synthesizer is
|
67 |
|
|
|
68 |
8 |
plutonium |
signal ftw_accu : std_logic_vector(ftw_width-1 downto 0);
|
69 |
|
|
signal phase : std_logic_vector(PHASE_WIDTH-1 downto 0);
|
70 |
|
|
signal lut_in : std_logic_vector(PHASE_WIDTH-3 downto 0);
|
71 |
|
|
signal lut_out : std_logic_vector(AMPL_WIDTH-1 downto 0);
|
72 |
|
|
signal lut_out_delay : std_logic_vector(AMPL_WIDTH-1 downto 0);
|
73 |
|
|
signal lut_out_inv_delay : std_logic_vector(AMPL_WIDTH-1 downto 0);
|
74 |
|
|
signal quadrant_2_or_4 : std_logic;
|
75 |
|
|
signal quadrant_3_or_4 : std_logic;
|
76 |
|
|
signal quadrant_3_or_4_delay : std_logic;
|
77 |
3 |
plutonium |
signal quadrant_3_or_4_2delay : std_logic;
|
78 |
|
|
|
79 |
|
|
begin
|
80 |
|
|
phase_o <= phase;
|
81 |
|
|
quadrant_2_or_4 <= phase(PHASE_WIDTH-2);
|
82 |
|
|
quadrant_3_or_4 <= phase(PHASE_WIDTH-1);
|
83 |
|
|
|
84 |
|
|
lut_in <= phase(PHASE_WIDTH-3 downto 0) when quadrant_2_or_4 = '0' else conv_std_logic_vector(2**(PHASE_WIDTH-2)-conv_integer(phase(PHASE_WIDTH-3 downto 0)), PHASE_WIDTH-2);
|
85 |
8 |
plutonium |
ampl_o <= lut_out_delay when quadrant_3_or_4_2delay = '0' else lut_out_inv_delay;
|
86 |
3 |
plutonium |
|
87 |
|
|
process (clk_i, rst_i)
|
88 |
|
|
begin
|
89 |
|
|
if rst_i = '1' then
|
90 |
|
|
ftw_accu <= (others => '0');
|
91 |
|
|
phase <= (others => '0');
|
92 |
8 |
plutonium |
lut_out <= (others => '0');
|
93 |
|
|
lut_out_delay <= (others => '0');
|
94 |
|
|
lut_out_inv_delay <= (others => '0');
|
95 |
|
|
quadrant_3_or_4_delay <= '0';
|
96 |
|
|
quadrant_3_or_4_2delay <= '0';
|
97 |
3 |
plutonium |
elsif clk_i'event and clk_i = '1' then
|
98 |
8 |
plutonium |
ftw_accu <= ftw_accu + ftw_i;
|
99 |
|
|
phase <= ftw_accu(ftw_width-1 downto ftw_width-PHASE_WIDTH) + phase_i;
|
100 |
3 |
plutonium |
if quadrant_2_or_4 = '1' and phase(PHASE_WIDTH - 3 downto 0) = conv_std_logic_vector (0, PHASE_WIDTH - 2) then
|
101 |
|
|
lut_out <= conv_std_logic_vector(2**(AMPL_WIDTH - 1) - 1, AMPL_WIDTH);
|
102 |
|
|
else
|
103 |
|
|
lut_out <= sine_lut(conv_integer(lut_in));
|
104 |
|
|
end if;
|
105 |
|
|
quadrant_3_or_4_delay <= quadrant_3_or_4;
|
106 |
|
|
quadrant_3_or_4_2delay <= quadrant_3_or_4_delay;
|
107 |
|
|
lut_out_inv_delay <= conv_std_logic_vector(-1*conv_integer(lut_out), AMPL_WIDTH);
|
108 |
|
|
lut_out_delay <= lut_out;
|
109 |
|
|
end if;
|
110 |
|
|
end process;
|
111 |
|
|
|
112 |
|
|
end dds_synthesizer_arch;
|