Subversion Repositories debouncer_vhdl

--------------------------------------------------------------------------------

Release 13.1 Trace  (nt)

Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.

C:\Xilinx\13.1\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 2 -n

3 -fastpaths -xml debounce_atlys_top.twx debounce_atlys_top.ncd -o

debounce_atlys_top.twr debounce_atlys_top.pcf -ucf debounce_atlys.ucf

Design file:              debounce_atlys_top.ncd

Physical constraint file: debounce_atlys_top.pcf

Device,package,speed:     xc6slx45,csg324,C,-2 (PRODUCTION 1.18 2011-04-07)

Report level:             verbose report

Environment Variable      Effect

--------------------      ------

NONE                      No environment variables were set

--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.

INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths

   option. All paths that are not constrained will be reported in the

   unconstrained paths section(s) of the report.

INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on

   a 50 Ohm transmission line loading model.  For the details of this model,

   and for more information on accounting for different loading conditions,

   please see the device datasheet.

Data Sheet report:

-----------------

All values displayed in nanoseconds (ns)

Setup/Hold to clock gclk_i

------------+------------+------------+------------+------------+------------------+--------+

            |Max Setup to|  Process   |Max Hold to |  Process   |                  | Clock  |

Source      | clk (edge) |   Corner   | clk (edge) |   Corner   |Internal Clock(s) | Phase  |

------------+------------+------------+------------+------------+------------------+--------+

sw_i<0>     |    4.897(R)|      SLOW  |   -2.640(R)|      FAST  |gclk_i_BUFGP      |   0.000|

sw_i<1>     |    5.976(R)|      SLOW  |   -3.369(R)|      FAST  |gclk_i_BUFGP      |   0.000|

sw_i<2>     |    6.081(R)|      SLOW  |   -3.407(R)|      FAST  |gclk_i_BUFGP      |   0.000|

sw_i<3>     |    5.313(R)|      SLOW  |   -2.891(R)|      FAST  |gclk_i_BUFGP      |   0.000|

sw_i<4>     |    2.578(R)|      SLOW  |   -1.340(R)|      SLOW  |gclk_i_BUFGP      |   0.000|

sw_i<5>     |    3.922(R)|      SLOW  |   -2.152(R)|      FAST  |gclk_i_BUFGP      |   0.000|

sw_i<6>     |    3.293(R)|      SLOW  |   -1.813(R)|      FAST  |gclk_i_BUFGP      |   0.000|

------------+------------+------------+------------+------------+------------------+--------+

Clock gclk_i to Pad

------------+-----------------+------------+-----------------+------------+------------------+--------+

            |Max (slowest) clk|  Process   |Min (fastest) clk|  Process   |                  | Clock  |

Destination |  (edge) to PAD  |   Corner   |  (edge) to PAD  |   Corner   |Internal Clock(s) | Phase  |

------------+-----------------+------------+-----------------+------------+------------------+--------+

dbg_o<7>    |        11.316(R)|      SLOW  |         4.892(R)|      FAST  |gclk_i_BUFGP      |   0.000|

dbg_o<8>    |        11.472(R)|      SLOW  |         4.944(R)|      FAST  |gclk_i_BUFGP      |   0.000|

dbg_o<9>    |        11.204(R)|      SLOW  |         4.794(R)|      FAST  |gclk_i_BUFGP      |   0.000|

dbg_o<10>   |        11.504(R)|      SLOW  |         4.993(R)|      FAST  |gclk_i_BUFGP      |   0.000|

dbg_o<11>   |        11.865(R)|      SLOW  |         5.220(R)|      FAST  |gclk_i_BUFGP      |   0.000|

dbg_o<12>   |        12.635(R)|      SLOW  |         5.653(R)|      FAST  |gclk_i_BUFGP      |   0.000|

dbg_o<13>   |        12.428(R)|      SLOW  |         5.522(R)|      FAST  |gclk_i_BUFGP      |   0.000|

dbg_o<14>   |        13.576(R)|      SLOW  |         6.221(R)|      FAST  |gclk_i_BUFGP      |   0.000|

led_o<0>    |         9.204(R)|      SLOW  |         3.688(R)|      FAST  |gclk_i_BUFGP      |   0.000|

led_o<1>    |         9.148(R)|      SLOW  |         3.672(R)|      FAST  |gclk_i_BUFGP      |   0.000|

led_o<2>    |         9.367(R)|      SLOW  |         3.814(R)|      FAST  |gclk_i_BUFGP      |   0.000|

led_o<3>    |         9.812(R)|      SLOW  |         4.033(R)|      FAST  |gclk_i_BUFGP      |   0.000|

led_o<4>    |        10.245(R)|      SLOW  |         4.270(R)|      FAST  |gclk_i_BUFGP      |   0.000|

led_o<5>    |        16.830(R)|      SLOW  |         8.118(R)|      FAST  |gclk_i_BUFGP      |   0.000|

led_o<6>    |        11.879(R)|      SLOW  |         5.161(R)|      FAST  |gclk_i_BUFGP      |   0.000|

------------+-----------------+------------+-----------------+------------+------------------+--------+

Clock to Setup on destination clock gclk_i

---------------+---------+---------+---------+---------+

               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|

Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|

---------------+---------+---------+---------+---------+

gclk_i         |    4.423|         |         |         |

---------------+---------+---------+---------+---------+

Pad to Pad

---------------+---------------+---------+

Source Pad     |Destination Pad|  Delay  |

---------------+---------------+---------+

sw_i<0>        |dbg_o<0>       |   15.462|

sw_i<1>        |dbg_o<1>       |   16.552|

sw_i<2>        |dbg_o<2>       |   16.755|

sw_i<3>        |dbg_o<3>       |    9.229|

sw_i<4>        |dbg_o<4>       |    7.978|

sw_i<5>        |dbg_o<5>       |    8.889|

sw_i<6>        |dbg_o<6>       |    9.058|

---------------+---------------+---------+

Analysis completed Thu Aug 11 21:32:01 2011

--------------------------------------------------------------------------------

Trace Settings:

-------------------------

Trace Settings

Peak Memory Usage: 175 MB