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jcorley |
//-------------------------------------------------------------------------
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//
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// File name : ldpc_vn.v
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// Title :
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// :
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// Purpose : Variable node holder/message calculator. Loads llr
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// : data serially, and controls RAM's. This module is
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// : written to be as compact as possible, since it is
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// : instantiated a large number of times. Some outputs,
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// : especially RAM controls, are not registered.
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//
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// ----------------------------------------------------------------------
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// Revision History :
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// ----------------------------------------------------------------------
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// Ver :| Author :| Mod. Date :| Changes Made:
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// v1.0 | JTC :| 2008/07/02 :|
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// ----------------------------------------------------------------------
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`timescale 1ns/10ps
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module ldpc_vn #(
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parameter FOLDFACTOR = 1,
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parameter LLRWIDTH = 6
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)(
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input clk,
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input rst,
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// LLR I/O
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input llr_access,
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input[7+FOLDFACTOR-1:0] llr_addr,
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input llr_din_we,
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input[LLRWIDTH-1:0] llr_din,
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output[LLRWIDTH-1:0] llr_dout,
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// message control
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input iteration,
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input first_half,
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input first_iteration, // ignore upmsgs
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input we_vnmsg,
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input disable_vn,
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input[7+FOLDFACTOR-1:0] addr_vn,
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// message I/O
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input[LLRWIDTH-1:0] sh_msg,
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output[LLRWIDTH-1:0] vn_msg,
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// Attached RAM, holds iteration number, original LLR and message sum
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output[7+FOLDFACTOR-1:0] vnram_wraddr,
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output[7+FOLDFACTOR-1:0] vnram_rdaddr,
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output upmsg_we,
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output[2*LLRWIDTH+4:0] upmsg_din,
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input[2*LLRWIDTH+4:0] upmsg_dout
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);
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// Split RAM outputs
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wire[LLRWIDTH-1:0] llr_orig;
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wire[LLRWIDTH+3:0] stored_msg_sum;
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wire stored_iteration;
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assign llr_orig = upmsg_dout[LLRWIDTH-1:0];
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assign stored_msg_sum = upmsg_dout[2*LLRWIDTH+3:LLRWIDTH];
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assign stored_iteration = upmsg_dout[2*LLRWIDTH+4];
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/************************************************************
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* Add 1's complement numbers, assume overflow not possible *
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************************************************************/
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function[LLRWIDTH+3:0] AddNewMsg( input[LLRWIDTH+3:0] a,
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input[LLRWIDTH-1:0] b );
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reg signa;
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reg signb;
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reg[LLRWIDTH+2:0] maga;
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reg[LLRWIDTH+2:0] magb;
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reg[LLRWIDTH+2:0] sum;
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reg[LLRWIDTH+2:0] diffa;
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reg[LLRWIDTH+2:0] diffb;
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reg add;
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reg b_big;
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reg sign;
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reg[LLRWIDTH+3:0] result;
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begin
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// strip out magnitude and sign bits
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signa = a[LLRWIDTH+3];
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signb = b[LLRWIDTH-1];
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maga = a[LLRWIDTH+2:0];
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magb = { 4'b0000, b[LLRWIDTH-2:0] };
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// basic calculations
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sum = maga + magb;
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diffa = maga - magb;
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diffb = magb - maga;
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// control bits
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add = signa==signb;
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b_big = maga<magb;
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sign = b_big ? signb : signa;
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if( add )
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result = { sign, sum };
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else if( b_big )
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result = { sign, diffb };
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else
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result = { sign, diffa };
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AddNewMsg = result;
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end
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endfunction
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/*************************************************
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* Saturate message to fewer bits before passing *
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*************************************************/
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function[LLRWIDTH-1:0] SaturateMsg( input[LLRWIDTH+3:0] a );
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begin
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if( a[LLRWIDTH+2:LLRWIDTH-1] != 4'b0000 )
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SaturateMsg[LLRWIDTH-2:0] = { (LLRWIDTH-1){1'b1} };
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else
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SaturateMsg[LLRWIDTH-2:0] = a[LLRWIDTH-2:0];
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SaturateMsg[LLRWIDTH-1] = a[LLRWIDTH+3];
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end
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endfunction
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/********************************************
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* Delays to align controls with RAM output *
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********************************************/
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localparam RAM_LATENCY = 2;
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integer loopvar1;
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reg[7+FOLDFACTOR-1:0] vnram_rdaddr_int;
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reg[LLRWIDTH-1:0] sh_msg_del[0:RAM_LATENCY-1];
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reg we_vnmsg_del[0:RAM_LATENCY-1];
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reg[7+FOLDFACTOR-1:0] vnram_rdaddr_del[0:RAM_LATENCY-1];
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reg disable_del[0:RAM_LATENCY-1];
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wire[LLRWIDTH-1:0] sh_msg_aligned_ram;
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wire we_vnmsg_aligned_ram;
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wire[7+FOLDFACTOR-1:0] vnram_rdaddr_aligned_ram;
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wire disable_aligned_ram;
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reg recycle_result;
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// mux in alternative address for final read-out
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assign vnram_rdaddr = vnram_rdaddr_int;
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always @( * ) vnram_rdaddr_int <= #1 llr_access ? llr_addr : addr_vn;
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assign sh_msg_aligned_ram = sh_msg_del[RAM_LATENCY-1];
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assign we_vnmsg_aligned_ram = we_vnmsg_del[RAM_LATENCY-1];
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assign vnram_rdaddr_aligned_ram = vnram_rdaddr_del[RAM_LATENCY-1];
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assign disable_aligned_ram = disable_del[RAM_LATENCY-1];
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always @( posedge rst, posedge clk )
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if( rst )
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begin
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for( loopvar1=0; loopvar1<RAM_LATENCY; loopvar1=loopvar1+1 )
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begin
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sh_msg_del[loopvar1] <= 0;
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we_vnmsg_del[loopvar1] <= 0;
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vnram_rdaddr_del[loopvar1] <= 0;
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disable_del[loopvar1] <= 0;
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end
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recycle_result <= 0;
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end
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else
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begin
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sh_msg_del[0] <= sh_msg;
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we_vnmsg_del[0] <= we_vnmsg;
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vnram_rdaddr_del[0] <= vnram_rdaddr_int;
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disable_del[0] <= disable_vn;
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for( loopvar1=1; loopvar1<RAM_LATENCY; loopvar1=loopvar1+1 )
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begin
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sh_msg_del[loopvar1] <= sh_msg_del[loopvar1 -1];
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we_vnmsg_del[loopvar1] <= we_vnmsg_del[loopvar1 -1];
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vnram_rdaddr_del[loopvar1] <= vnram_rdaddr_del[loopvar1 -1];
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disable_del[loopvar1] <= disable_del[loopvar1 -1];
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end
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// Use previous result rather than the RAM contents for two adjacent
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// writes to the same address
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recycle_result <= (vnram_rdaddr_aligned_ram==vnram_rdaddr_del[RAM_LATENCY-2]) &
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we_vnmsg_aligned_ram & we_vnmsg_del[RAM_LATENCY-2];
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end
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/************************
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* Message calculations *
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************************/
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// Add initial LLR to message offset (except for first iteration)
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reg[LLRWIDTH+3:0] msg0_norst;
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wire[LLRWIDTH+3:0] msg0;
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reg[LLRWIDTH-1:0] msg1;
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wire start_new_upmsg;
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reg rst_msg0;
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wire[LLRWIDTH+3:0] msg_sum;
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reg[LLRWIDTH+3:0] msg_sum_reg;
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// Add upmsg to the result, except:
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// - during first iteration, since no upmsg exists
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// - first message of each new iteration, where upmsg needs to be reset
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assign start_new_upmsg = (stored_iteration!=iteration) & we_vnmsg_aligned_ram;
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assign msg0 = rst_msg0 ? 0 : msg0_norst;
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always @( posedge clk, posedge rst )
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if( rst )
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begin
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msg0_norst <= 0;
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rst_msg0 <= 0;
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msg1 <= 0;
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msg_sum_reg <= 0;
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end
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else
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begin
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// msg0 = sum of received upstream messages
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// clear msg0 when beginning a new set of upstream messages
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msg0_norst <= recycle_result ? msg_sum : stored_msg_sum;
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rst_msg0 <= start_new_upmsg & ~recycle_result;
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msg1 <= (llr_access || first_half) ? llr_orig : sh_msg_aligned_ram;
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msg_sum_reg <= msg_sum;
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end
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// When creating downstream messages, or preparing final result:
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// msg_sum = llr + sum of messages
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// When receiving upstream messages:
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// msg_sum = new message + sum of messages
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assign msg_sum = AddNewMsg( msg0, msg1 );
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/****************************************
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* Delay controls to align with msg_sum *
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****************************************/
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localparam CALC_LATENCY = 2;
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integer loopvar2;
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reg we_vnmsg_del2[0:RAM_LATENCY-1];
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reg[7+FOLDFACTOR-1:0] vnram_rdaddr_del2[0:RAM_LATENCY-1];
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reg[LLRWIDTH-1:0] llrram_dout_del2[0:RAM_LATENCY-1];
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reg disable_del2[0:RAM_LATENCY-1];
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wire we_vnmsg_aligned_msg;
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wire[7+FOLDFACTOR-1:0] vnram_rdaddr_aligned_msg;
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wire[LLRWIDTH-1:0] llrram_dout_aligned_msg;
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wire disable_aligned_msg;
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assign we_vnmsg_aligned_msg = we_vnmsg_del2[RAM_LATENCY-1];
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assign vnram_rdaddr_aligned_msg = vnram_rdaddr_del2[RAM_LATENCY-1];
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assign llrram_dout_aligned_msg = llrram_dout_del2[RAM_LATENCY-1];
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assign disable_aligned_msg = disable_del2[RAM_LATENCY-1];
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always @( posedge rst, posedge clk )
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if( rst )
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begin
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for( loopvar2=0; loopvar2<RAM_LATENCY; loopvar2=loopvar2+1 )
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begin
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we_vnmsg_del2[loopvar2] <= 0;
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vnram_rdaddr_del2[loopvar2] <= 0;
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llrram_dout_del2[loopvar2] <= 0;
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disable_del2[loopvar2] <= 0;
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end
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end
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else
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begin
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we_vnmsg_del2[0] <= we_vnmsg_aligned_ram;
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vnram_rdaddr_del2[0] <= vnram_rdaddr_aligned_ram;
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llrram_dout_del2[0] <= llr_orig;
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disable_del2[0] <= disable_aligned_ram;
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for( loopvar2=1; loopvar2<RAM_LATENCY; loopvar2=loopvar2+1 )
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begin
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we_vnmsg_del2[loopvar2] <= we_vnmsg_del2[loopvar2 -1];
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vnram_rdaddr_del2[loopvar2] <= vnram_rdaddr_del2[loopvar2 -1];
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llrram_dout_del2[loopvar2] <= llrram_dout_del2[loopvar2 -1];
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disable_del2[loopvar2] <= disable_del2[loopvar2 -1];
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end
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end
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/*******************************
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* Write message totals to RAM *
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*******************************/
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reg[7+FOLDFACTOR-1:0] vnram_wraddr_int;
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reg[LLRWIDTH-1:0] new_llr;
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reg new_iteration;
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reg[LLRWIDTH+3:0] new_msg_sum;
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reg upmsg_we_int;
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assign vnram_wraddr = vnram_wraddr_int;
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assign upmsg_din = { new_iteration, new_msg_sum, new_llr };
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assign upmsg_we = upmsg_we_int;
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always @( posedge rst, posedge clk )
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if( rst )
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begin
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vnram_wraddr_int <= 0;
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new_llr <= 0;
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new_msg_sum <= 0;
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new_iteration <= 0;
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upmsg_we_int <= 1;
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end
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else
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begin
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// mux and register outputs
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vnram_wraddr_int <= #1 llr_access ? llr_addr : vnram_rdaddr_aligned_msg;
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new_llr <= #1 llr_access ? llr_din : llrram_dout_aligned_msg;
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new_msg_sum <= #1 llr_access ? 0 : msg_sum_reg;
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new_iteration <= #1 llr_access | iteration;
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upmsg_we_int <= #1 ~(llr_din_we | (we_vnmsg_aligned_msg & ~disable_aligned_msg));
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end
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/*****************************************************************
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* Saturate message to fewer bits for message passing and output *
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*****************************************************************/
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reg[LLRWIDTH-1:0] vn_msg_int;
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assign llr_dout = vn_msg_int;
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assign vn_msg = vn_msg_int;
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always @( posedge rst, posedge clk )
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if( rst )
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vn_msg_int <= 0;
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else
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vn_msg_int <= SaturateMsg(msg_sum_reg);
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endmodule
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