Subversion Repositories ecpu_alu

# ECPU 0.1.alpha

# ==============

#

# Background

# ========

# Resurrected university project originally written in VHDL.

# Converted to Verilog by hand and fixed bugs.

#

# Modifications made in verilog post-conversion:

# - New barrel shifter

# - Reviewed opcode list

# - Enhanced testbench to allow for random stimulus (verilog only tb)

# - Tested using Icarus

#

# Currently checking for synthesis:

# - Passes synthesis checks using "veriwell ... +synopsys"

#

# Features

# ========

# * 15 working opcodes/functions :

#     cADD_AB

#     cINC_A

#     cINC_B

#     cSUB_AB

#     cCMP_AB   - Same as Xor

#     cASL_AbyB - Uses last three bits of B (barrel shift)

#     cASR_AbyB - Uses last three bits of B (barrel shift)

#     cCLR      - Clear outputs

#     cDEC_A

#     cDEC_B

#     cMUL_AB   - not implemented [yet]

#     cCPL_A

#     cAND_AB

#     cOR_AB

#     cXOR_AB

#     cCPL_B

#

# * Flags C, V, Z - not implemented [yet]

#

#     C         - TBD

#     V         - TBD

#     Z         - TBD

#

# Simulating

# ========

#

#   1) Run the setup.sh script in the top level directory

#       source ./setup.sh

#

#   2) Modify sim/alu_test.txt as required (or leave as is for first time demo)

#

#   3) Execute the run script (from the sim directory)

#

#         unix_prompt% cd sim

#         unix_prompt% ./runit [options]

#

#

# Available options:

#

# * Any valid iverilog option

#

# * Use -D and the following defines to modify testbench behaviour

#

#

#   DECIMAL_DISPLAY                         Display information in decimal

#   HEX_DISPLAY                             Display information in hex

#   BINARY_DISPLAY                          Display information in binary

#

#   RANDOM=   Ignore alu_test.txt and generate

#                                           $random stimulus.

#

#   DEBUG_ALU_TB                            Print out extra information for debug

#

#   FORCE_A=                         Force ALU input A to a constant value

#   FORCE_B=                         Force ALU input B to a constant value

#   FORCE_OPCODE=                   Force ALU input S to a constant string

#   FORCE_CLR=                         Force ALU input CLR to a constant bit

#

#   STOP_ON_ERROR                           Stop on the first error encountered

#

#   CREATE_SIGNAL_LOG                       Create a log file containing IO states per

#                                           posedge clk

#

#

# example:

#   % ./runit -DRANDOM=10000 -DSTOP_ON_ERROR &> log

#

#