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## Generated SDC file "fpmult.sdc"

## Copyright (C) 1991-2010 Altera Corporation

## Your use of Altera Corporation's design tools, logic functions

## and other software and tools, and its AMPP partner logic

## functions, and any output files from any of the foregoing

## (including device programming or simulation files), and any

## associated documentation or information are expressly subject

## to the terms and conditions of the Altera Program License

## Subscription Agreement, Altera MegaCore Function License

## Agreement, or other applicable license agreement, including,

## without limitation, that your use is for the sole purpose of

## programming logic devices manufactured by Altera and sold by

## Altera or its authorized distributors.  Please refer to the

## applicable agreement for further details.

## VENDOR  "Altera"

## PROGRAM "Quartus II"

## VERSION "Version 10.1 Build 153 11/29/2010 SJ Web Edition"

## DATE    "Sun Jan 30 18:51:15 2011"

##

## DEVICE  "EP2C20F484C7"

##

#**************************************************************

# Time Information

#**************************************************************

set_time_format -unit ns -decimal_places 3

#**************************************************************

# Create Clock

#**************************************************************

create_clock -name {altera_reserved_tck} -period 20.000 -waveform { 0.000 10.000 } [get_ports { altera_reserved_tck }]

#**************************************************************

# Create Generated Clock

#**************************************************************

#**************************************************************

# Set Clock Latency

#**************************************************************

#**************************************************************

# Set Clock Uncertainty

#**************************************************************

#**************************************************************

# Set Input Delay

#**************************************************************

#**************************************************************

# Set Output Delay

#**************************************************************

#**************************************************************

# Set Clock Groups

#**************************************************************

set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]

#**************************************************************

# Set False Path

#**************************************************************

#**************************************************************

# Set Multicycle Path

#**************************************************************

#**************************************************************

# Set Maximum Delay

#**************************************************************

#**************************************************************

# Set Minimum Delay

#**************************************************************

#**************************************************************

# Set Input Transition

#**************************************************************