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[/] [epc_rfid_transponder/] [trunk/] [flashmemTID.vhd] - Blame information for rev 2

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1 2 erwing
-------------------------------------------------------------------------------
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--     Politecnico di Torino                                              
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--     Dipartimento di Automatica e Informatica             
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------     
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--
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--     Title          : Flash Memory TID
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--
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--     File name      : flashmemTID.vhd 
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--
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--     Description    : Flash memory model.  
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--
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--     Author         : Paolo Bernardi <paolo.bernardi@polito.it>
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--
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--     Rev. History   : Erwing Sanchez  -- 17/07/06
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--                              - Ready/busy input removed because not used
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--                              - "Bits" generic removed
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--                              - RP input removed
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--                              - Command codes changed to work with Data = 16
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--                      E.R. Sanchez   -- 13/10/06     
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--                              - Include Parameters & Initialization
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-------------------------------------------------------------------------------            
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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use IEEE.std_logic_textio.all;
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use STD.TEXTIO.all;
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entity Flash_MeM_TID is
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  generic (
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    Words : integer := 8;           -- number of addresses
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    Addr  : integer := 2;  -- number of pins reserved for addresses
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    Data  : integer := 16
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    );
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  port (
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    A  : in  std_logic_vector(Addr-1 downto 0);  -- Address inputs
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    D  : in  std_logic_vector(Data-1 downto 0);  -- Data input
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    Q  : out std_logic_vector(Data-1 downto 0);  -- Data output
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    G  : in  std_logic;                 -- Output enable
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    W  : in  std_logic;                 -- Write  enable
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    RC : in  std_logic;                 -- Row/Column address select
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    st : out std_logic                  -- Interface reset
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    );
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end Flash_MeM_TID;
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--synopsys synthesis_on
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architecture Behavioural of Flash_MeM_TID is
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--synopsys synthesis_off
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  type   Flash_Type is array (0 to Words-1) of std_logic_vector(Data-1 downto 0);
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  signal Mem : Flash_Type := (others => (others => '1'));
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  signal Addr_int : std_logic_vector((2*Addr)-1 downto 0);
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  signal Data_int : std_logic_vector(Data-1 downto 0);
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  signal program         : std_logic := '0';
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  signal erase           : std_logic := '0';
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  signal i               : natural range Words-1 downto 0;
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  signal status_register : std_logic_vector(Data-1 downto 0);
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  signal status          : std_logic;
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  signal InitIsDoneFlag  : std_logic := '0';
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  function resetVector (dim : natural) return std_logic_vector is
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    variable vectorOut : std_logic_vector(dim -1 downto 0);
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    variable i         : natural range dim downto 0;
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  begin
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    for i in 0 to dim-1 loop
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      vectorOut(i) := '0';
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    end loop;
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    return vectorOut;
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  end resetVector;
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  function erase_mem (mem : Flash_Type) return Flash_Type is
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    variable mem_out : Flash_Type;
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    variable i       : natural range Words-1 downto 0;
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  begin
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    for i in 0 to Words-1 loop
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      Mem_out(i) := (others => '1');    --"11111111";
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    end loop;
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    return mem_out;
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  end erase_mem;
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  --synopsys synthesis_on
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begin  --BEHAVIOURAL
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  --synopsys synthesis_off
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  write_first : process (RC)
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  begin
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    if RC'event and RC = '0' then
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      Addr_int(Addr-1 downto 0) <= A;
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    end if;
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  end process write_first;
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  write_second : process (RC)
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  begin
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    if RC'event and RC = '1' then
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      Addr_int((2*Addr)-1 downto Addr) <= A;
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    end if;
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  end process write_second;
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  w_data : process (W)
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  begin
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    if W'event and W = '1' then
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      if program = '1' then
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        Mem(conv_integer(unsigned(Addr_int))) <= D after 50 ns;
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        status_register                       <= conv_std_logic_vector(64, Data);  --"01000000"
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        Data_int                              <= resetVector(Data_int'length);
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        st                                    <= '0';
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      elsif erase = '1' then
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        Mem      <= erase_mem(Mem) after 750000000 ns;
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        Data_int <= resetVector(Data_int'length);
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        st       <= '1'            after 750000000 ns;
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      else
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        Data_int        <= D;
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        status_register <= (others => '0');  --"00000000";
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        st              <= '0';
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      end if;
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    end if;
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  end process w_data;
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  read_data : process (G)
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  begin
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    if G'event and G = '0' then
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      if status = '0' then
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        Q <= Mem(conv_integer(unsigned(Addr_int))) after 50 ns;
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      else
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        Q <= status_register after 750000000 ns;
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      end if;
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    elsif G'event and G = '1' then
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      Q <= (others => 'U') after 50 ns;  -- "UUUUUUUU"
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    end if;
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  end process read_data;
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  decode : process (Data_int)
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  begin
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    case conv_integer(Data_int) is
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      when 64 =>                        -- "01000000"  program
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        program <= '1';
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        erase   <= '0';
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        status  <= '0';
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      when 32 =>                        -- "00100000"  erase
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        program <= '0';
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        erase   <= '1';
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        status  <= '0';
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      when 112 =>                       -- "01110000"  read status reg
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        program <= '0';
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        erase   <= '0';
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        status  <= '1';
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      when others =>
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        program <= '0';
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        erase   <= '0';
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        status  <= '0';
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    end case;
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  end process decode;
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--  -- purpose: Load Memory from file  
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--  load_memory : process(A, D, G, W, RC, InitIsDoneFlag)
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--    file init_mem_file       : text open read_mode is "meminit.txt";
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--    variable inline, outline : line;
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--    variable add             : natural;
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--    variable c               : character;
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--    variable Mem_var         : Flash_Type;
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--  begin  -- process load_memory
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--    if InitIsDoneFlag = '0' then
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--      -- Clear Memory
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--      for i in 0 to Words-1 loop
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--        Mem_var(i) := (others => '0');
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--      end loop;  -- i
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--      -- Load
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--      while not endfile(init_mem_file) loop
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--        readline(init_mem_file, inline);
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--        read(inline, add);
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--        read(inline, c);
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--        if c /= ':' then
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--          write(outline, string'("Syntax Error"));
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--          writeline(output, outline);
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--          assert false report "Mem Loader Aborted" severity failure;
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--        end if;
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--        for i in (Data-1) downto 0 loop
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--          read(inline, c);
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--          if c = '1' then
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--            Mem_var(add)(i) := '1';
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--          elsif c = '0' then
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--            Mem_var(add)(i) := '0';
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--          else
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--            write(outline, string'("Invalid Character-Set to '0'"));
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--            writeline(output, outline);
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--            Mem_var(add)(i) := '0';
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--          end if;
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--        end loop;  -- i
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--      end loop;
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--      Mem <= Mem_var;
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--      InitIsDoneFlag <= '1';
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--    end if;
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--  end process load_memory;
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--synopsys synthesis_on
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end Behavioural;
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--synopsys synthesis_off
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configuration CFG_Flash_MeM_TID of Flash_MeM_TID is
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  for Behavioural
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  end for;
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end CFG_Flash_MeM_TID;
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--synopsys synthesis_on

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